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Demo w/ SPI if works

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This commit is contained in:
jaseg 2021-06-27 13:46:07 +02:00
parent f5f25e7d06
commit 84bf26f1dc
9 changed files with 108 additions and 42 deletions
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21
Artix-7-HDMI-processing.xpr
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@ -49,13 +49,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="3"/> <Option Name="WTXSimExportSim" Val="4"/>
<Option Name="WTModelSimExportSim" Val="3"/> <Option Name="WTModelSimExportSim" Val="4"/>
<Option Name="WTQuestaExportSim" Val="3"/> <Option Name="WTQuestaExportSim" Val="4"/>
<Option Name="WTIesExportSim" Val="3"/> <Option Name="WTIesExportSim" Val="4"/>
<Option Name="WTVcsExportSim" Val="3"/> <Option Name="WTVcsExportSim" Val="4"/>
<Option Name="WTRivieraExportSim" Val="3"/> <Option Name="WTRivieraExportSim" Val="4"/>
<Option Name="WTActivehdlExportSim" Val="3"/> <Option Name="WTActivehdlExportSim" Val="4"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
@ -68,6 +68,13 @@
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PPRDIR/src/edge_cleaner.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/src/spi_regfile.v"> <File Path="$PPRDIR/src/spi_regfile.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>

16
constraints/NexysVideo.xdc
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@ -39,14 +39,14 @@ set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_t
set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2] set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
# DEBUG on JA # DEBUG on JA
set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1] set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { sck }]; #IO_L10N_T1_D15_14 Sch=ja[1]
set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2] set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ncs }]; #IO_L10P_T1_D14_14 Sch=ja[2]
set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3] set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { sdi }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4] set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { sdo }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7] set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[0] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8] set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[1] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9] set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[2] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10 set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { debug_pmod[3] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10
##Switches ##Switches
set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS25 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0] set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS25 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]

19
src/edge_cleaner.v Normal file
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@ -0,0 +1,19 @@
module edge_cleaner(
input clk,
input in,
output reg out
);
reg [7:0] sr;
always @(posedge clk) begin
sr <= {sr[6:0], in};
if (sr == 8'hff) begin
out <= 1;
end else if (sr == 8'h00) begin
out <= 0;
end
end
endmodule

20
src/hdmi_design.vhd
View file

@ -58,7 +58,12 @@ entity hdmi_design is
-- Control signals -- Control signals
led : out std_logic_vector(7 downto 0) :=(others => '0'); led : out std_logic_vector(7 downto 0) :=(others => '0');
sw : in std_logic_vector(7 downto 0) :=(others => '0'); sw : in std_logic_vector(7 downto 0) :=(others => '0');
debug_pmod : out std_logic_vector(7 downto 0) :=(others => '0'); debug_pmod : out std_logic_vector(3 downto 0) :=(others => '0');
sck : in std_logic;
ncs : in std_logic;
sdi : in std_logic;
sdo : out std_logic;
--HDMI input signals --HDMI input signals
hdmi_rx_cec : inout std_logic; hdmi_rx_cec : inout std_logic;
@ -167,6 +172,12 @@ architecture Behavioral of hdmi_design is
component proc_top is component proc_top is
Port ( clk : in STD_LOGIC; Port ( clk : in STD_LOGIC;
switches : in std_logic_vector(7 downto 0); switches : in std_logic_vector(7 downto 0);
sck : in std_logic;
ncs : in std_logic;
sdi : in std_logic;
sdo : out std_logic;
------------------ ------------------
-- Incoming pixels -- Incoming pixels
------------------ ------------------
@ -228,7 +239,7 @@ architecture Behavioral of hdmi_design is
signal io_debug : std_logic_vector(7 downto 0); signal io_debug : std_logic_vector(7 downto 0);
signal proc_debug : std_logic_vector(5 downto 0); signal proc_debug : std_logic_vector(5 downto 0);
begin begin
debug_pmod <= debug; debug_pmod <= debug(3 downto 0);
led <= debug; led <= debug;
debug(7 downto 6) <= io_debug(7 downto 6); debug(7 downto 6) <= io_debug(7 downto 6);
@ -307,6 +318,11 @@ i_hdmi_io: hdmi_io port map (
i_processing: proc_top Port map ( i_processing: proc_top Port map (
clk => pixel_clk, clk => pixel_clk,
switches => sw, switches => sw,
sck => sck,
ncs => ncs,
sdi => sdi,
sdo => sdo,
------------------ ------------------
-- Incoming pixels -- Incoming pixels
------------------ ------------------

31
src/spi_regfile.v
View file

@ -14,7 +14,8 @@ module spi_regfile(
output reg spi_cmd_begin, output reg spi_cmd_begin,
output reg spi_cmd_active, output reg spi_cmd_active,
output reg spi_cmd_step, output reg spi_cmd_step,
output reg [19:0] spi_cmd_idx output reg [19:0] spi_cmd_idx,
output [7:0] rxbuf_dbg
); );
reg [6:0] txbuf; reg [6:0] txbuf;
@ -24,14 +25,20 @@ reg last_ncs;
reg last_sck; reg last_sck;
reg load_data; reg load_data;
assign rxbuf_dbg = rxbuf;
wire sck_clean, sdi_clean, ncs_clean;
edge_cleaner sck_cleaner (.clk(clk), .in(sck), .out(sck_clean));
edge_cleaner sdi_cleaner (.clk(clk), .in(sdi), .out(sdi_clean));
edge_cleaner ncs_cleaner (.clk(clk), .in(ncs), .out(ncs_clean));
/* SPI mode 0: CPOL = 0, CPHA = 0. Initial SDO setup on falling ~CS edge */ /* SPI mode 0: CPOL = 0, CPHA = 0. Initial SDO setup on falling ~CS edge */
always @(posedge clk) begin always @(posedge clk) begin
spi_cmd_begin <= 0; spi_cmd_begin <= 0;
spi_cmd_step <= 0; spi_cmd_step <= 0;
load_data <= 0; last_ncs <= ncs_clean;
last_ncs <= ncs; last_sck <= sck_clean;
last_sck <= sck;
if (rst) begin if (rst) begin
is_cmd_word <= 1; is_cmd_word <= 1;
@ -39,39 +46,40 @@ always @(posedge clk) begin
spi_cmd_idx <= 0; spi_cmd_idx <= 0;
end else begin end else begin
if (last_ncs && !ncs) begin if (last_ncs && !ncs_clean) begin
txbuf <= spi_status_word[6:0]; txbuf <= spi_status_word[6:0];
sdo <= spi_status_word[7]; sdo <= spi_status_word[7];
rxbuf <= 8'h01; rxbuf <= 8'h01;
end end
if (!ncs) begin if (!ncs_clean) begin
if (!last_sck && sck) begin /* sampling edge */ if (!last_sck && sck_clean) begin /* sampling edge */
if (!rxbuf[7]) begin if (!rxbuf[7]) begin
rxbuf <= {rxbuf[6:0], sdi}; rxbuf <= {rxbuf[6:0], sdi_clean};
end else begin end else begin
rxbuf <= 8'h01; rxbuf <= 8'h01;
load_data <= 1; load_data <= 1;
if (is_cmd_word) begin if (is_cmd_word) begin
spi_cmd_word <= {rxbuf[6:0], sdi}; spi_cmd_word <= {rxbuf[6:0], sdi_clean};
is_cmd_word <= 0; is_cmd_word <= 0;
spi_cmd_active <= 1; spi_cmd_active <= 1;
spi_cmd_begin <= 1; spi_cmd_begin <= 1;
spi_cmd_idx <= 0; spi_cmd_idx <= 0;
end else begin end else begin
spi_data_out <= {rxbuf[6:0], sdi}; spi_data_out <= {rxbuf[6:0], sdi_clean};
spi_cmd_idx <= spi_cmd_idx+1; spi_cmd_idx <= spi_cmd_idx+1;
spi_cmd_step <= 1; spi_cmd_step <= 1;
end end
end end
end else if (last_sck && !sck) begin /* driving edge */ end else if (last_sck && !sck_clean) begin /* driving edge */
if (load_data) begin if (load_data) begin
sdo <= spi_data_in[7]; sdo <= spi_data_in[7];
txbuf <= spi_data_in[6:0]; txbuf <= spi_data_in[6:0];
load_data <= 0;
end else begin end else begin
sdo <= txbuf[6]; sdo <= txbuf[6];
@ -81,6 +89,7 @@ always @(posedge clk) begin
end else begin end else begin
spi_cmd_active <= 0; spi_cmd_active <= 0;
is_cmd_word <= 1;
end end
end end
end end

9
src/term_emu.v
View file

@ -8,7 +8,7 @@ module term_emu(
output reg in_byte_ack, output reg in_byte_ack,
output reg glyph_buffer_w_valid, output reg glyph_buffer_w_valid,
output [15:0] glyph_buffer_w_addr, output reg [15:0] glyph_buffer_w_addr,
output reg [19:0] glyph_buffer_w_data output reg [19:0] glyph_buffer_w_data
); );
@ -22,7 +22,7 @@ localparam ST_PARSE_TEXT = 9'b000000001,
ST_PARSE_INVAL = 9'b010000000; ST_PARSE_INVAL = 9'b010000000;
assign glyph_buffer_w_addr = (GLYPHMEM_W*glyph_y) + glyph_x; wire [15:0] glyph_buffer_w_addr_comp = (GLYPHMEM_W*glyph_y) + glyph_x;
reg [8:0] parser_state; reg [8:0] parser_state;
reg [3:0] cur_fg; reg [3:0] cur_fg;
@ -80,6 +80,10 @@ always @(posedge clk) begin
end else if (in_byte == 8'h0a) begin /* \n */ end else if (in_byte == 8'h0a) begin /* \n */
glyph_x <= 0; glyph_x <= 0;
glyph_buffer_w_valid <= 1;
glyph_buffer_w_data <= {1'b0, 1'b0, 2'b00, cur_bg, 4'b0000, in_byte};
glyph_buffer_w_addr <= glyph_buffer_w_addr_comp;
if (glyph_y != GLYPHMEM_H-1) begin if (glyph_y != GLYPHMEM_H-1) begin
glyph_y <= glyph_y + 1; glyph_y <= glyph_y + 1;
end end
@ -87,6 +91,7 @@ always @(posedge clk) begin
end else begin end else begin
glyph_buffer_w_valid <= 1; glyph_buffer_w_valid <= 1;
glyph_buffer_w_data <= {cur_underline, cur_bold, 2'b00, cur_bg, cur_fg, in_byte}; glyph_buffer_w_data <= {cur_underline, cur_bold, 2'b00, cur_bg, cur_fg, in_byte};
glyph_buffer_w_addr <= glyph_buffer_w_addr_comp;
if (glyph_x != GLYPHMEM_W-1) begin if (glyph_x != GLYPHMEM_W-1) begin
glyph_x <= glyph_x + 1; glyph_x <= glyph_x + 1;
end end

6
src/term_renderer.v
View file

@ -78,6 +78,7 @@ wire [11:0] gm_data_style = glyphmem_data[19:8];
reg [11:0] glyphmem_style_reg; reg [11:0] glyphmem_style_reg;
wire [3:0] gm_data_fgcolor = glyphmem_style_reg[3:0]; wire [3:0] gm_data_fgcolor = glyphmem_style_reg[3:0];
wire [3:0] gm_data_bgcolor = glyphmem_style_reg[7:4]; wire [3:0] gm_data_bgcolor = glyphmem_style_reg[7:4];
reg [3:0] last_bgcolor;
wire gm_data_bold = gm_data_style[10]; wire gm_data_bold = gm_data_style[10];
wire gm_data_underline = glyphmem_style_reg[11] && !newline_found; wire gm_data_underline = glyphmem_style_reg[11] && !newline_found;
reg newline_found; reg newline_found;
@ -87,7 +88,7 @@ assign out_hsync = in_hsync_last;
assign glyphmem_r_addr = (GLYPHMEM_W*glyph_y) + glyph_x; assign glyphmem_r_addr = (GLYPHMEM_W*glyph_y) + glyph_x;
wire px_data = glyph_sreg_out[FONT_GLYPH_W-1] || (gm_data_underline && px_y == FONT_GLYPH_H-2); wire px_data = glyph_sreg_out[FONT_GLYPH_W-1] || (gm_data_underline && px_y == FONT_GLYPH_H-2);
assign {out_red, out_green, out_blue} = color_palette(px_data ? gm_data_fgcolor : gm_data_bgcolor); assign {out_red, out_green, out_blue} = color_palette(newline_found ? last_bgcolor : (px_data ? gm_data_fgcolor : gm_data_bgcolor));
/* Core logic */ /* Core logic */
always @(posedge clk) begin always @(posedge clk) begin
@ -142,8 +143,9 @@ always @(posedge clk) begin
glyphmem_style_reg <= gm_data_style; glyphmem_style_reg <= gm_data_style;
glyph_x <= glyph_x + 1; glyph_x <= glyph_x + 1;
if (gm_data_glyph == 8'h0a) begin /* Newline character */ if (!newline_found && gm_data_glyph == 8'h0a) begin /* Newline character */
newline_found <= 1; newline_found <= 1;
last_bgcolor <= gm_data_bgcolor;
end end
end else begin end else begin

28
src/top.v
View file

@ -260,6 +260,8 @@ always @(posedge clk) begin
glyphmem_r_data <= glyphmem[glyphmem_r_addr]; glyphmem_r_data <= glyphmem[glyphmem_r_addr];
end end
wire [7:0] rxbuf_dbg;
spi_regfile spi_regfile_dut ( spi_regfile spi_regfile_dut (
.clk(clk), .rst(rst), .clk(clk), .rst(rst),
@ -273,7 +275,9 @@ spi_regfile spi_regfile_dut (
.spi_cmd_begin(spi_cmd_begin), .spi_cmd_begin(spi_cmd_begin),
.spi_cmd_active(spi_cmd_active), .spi_cmd_active(spi_cmd_active),
.spi_cmd_step(spi_cmd_step), .spi_cmd_step(spi_cmd_step),
.spi_cmd_idx(spi_cmd_idx) .spi_cmd_idx(spi_cmd_idx),
.rxbuf_dbg(rxbuf_dbg)
); );
term_emu #( term_emu #(
@ -367,22 +371,26 @@ window_matcher window_matcher_i (
ila_0 i_ila_0 ( ila_0 i_ila_0 (
.clk(clk), .clk(clk),
.probe0(win_x_dbg), .probe0({4'b0000, spi_cmd_word}),
.probe1(win_y_dbg), .probe1({4'b0000, rxbuf_dbg}),
.probe2(scan_x_dbg), .probe2(scan_x_dbg),
.probe3(scan_y_dbg), .probe3(scan_y_dbg),
.probe4({in_red, in_green, in_blue}), .probe4({4'b0000, spi_cmd_idx}),
.probe5(in_blank), .probe5(in_blank),
.probe6(in_hsync), .probe6(spi_cmd_step),
.probe7(in_vsync), .probe7(in_vsync),
.probe8(match_dbg), .probe8(spi_data_out),
.probe9(1'b0), .probe9(temu_in_valid),
.probe10(1'b0), .probe10(spi_cmd_begin),
.probe11(1'b0), .probe11(spi_cmd_active),
.probe12(win_blank), .probe12(win_blank),
.probe13(win_locked), .probe13(win_locked),
.probe14(out_data_en), .probe14(out_data_en),
.probe15(out_data_valid) .probe15(out_data_valid),
.probe16(sck),
.probe17(sdi),
.probe18(sdo),
.probe19(ncs)
); );
endmodule endmodule

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