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Fix window matcher for hsync/vsync convention

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This commit is contained in:
jaseg 2021-06-25 18:16:46 +02:00
parent 40301df014
commit 31aee929cc
6 changed files with 468 additions and 343 deletions
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74
Artix-7-HDMI-processing.xpr
View file

@ -42,20 +42,20 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="481"/>
<Option Name="WTXSimLaunchSim" Val="542"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="2"/>
<Option Name="WTModelSimExportSim" Val="2"/>
<Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="2"/>
<Option Name="WTVcsExportSim" Val="2"/>
<Option Name="WTRivieraExportSim" Val="2"/>
<Option Name="WTActivehdlExportSim" Val="2"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@ -273,8 +273,16 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/test_bench/window_matcher_tb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/test_bench/spi_regfile_tb.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@ -296,14 +304,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/test_bench/window_matcher_tb.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/test_bench/hdmi_test_generator/hdmi_ouput_test.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@ -382,7 +382,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="spi_regfile_tb"/>
<Option Name="TopModule" Val="window_matcher_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@ -408,6 +408,19 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="ila_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_0">
<File Path="$PSRCDIR/sources_1/ip/ila_0/ila_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="ila_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@ -438,6 +451,16 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="ila_0_synth_1" Type="Ft3:Synth" SrcSet="ila_0" Part="xc7a200tfbg484-1" ConstrsSet="ila_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
@ -456,6 +479,23 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="ila_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg484-1" ConstrsSet="ila_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>

31
src/top.v
View file

@ -303,6 +303,11 @@ term_renderer #(
.out_blue(win_blue)
);
wire [11:0] win_x_dbg;
wire [11:0] win_y_dbg;
wire [11:0] win_w_dbg;
wire [11:0] win_h_dbg;
window_matcher window_matcher_i (
.clk(clk),
.rst(rst),
@ -323,6 +328,11 @@ window_matcher window_matcher_i (
.win_locked(win_locked),
.win_w(win_w),
.win_h(win_h),
.win_x_dbg(win_x_dbg),
.win_y_dbg(win_y_dbg),
.win_w_dbg(win_w_dbg),
.win_h_dbg(win_h_dbg),
.out_data_en(out_data_en),
.out_data_valid(out_data_valid),
@ -340,4 +350,25 @@ window_matcher window_matcher_i (
.out_blue(out_blue)
);
ila_0 i_ila_0 (
.clk(clk),
.probe0(win_x_dbg),
.probe1(win_y_dbg),
.probe2(win_w_dbg),
.probe3(win_h_dbg),
.probe4({in_red, in_green, in_blue}),
.probe5(in_blank),
.probe6(in_hsync),
.probe7(in_vsync),
.probe8(win_hsync),
.probe9(win_vsync),
.probe10(win_blank),
.probe11(win_locked),
.probe12(out_data_en),
.probe13(out_data_valid),
.probe14(out_hsync),
.probe15(out_vsync)
);
endmodule

313
src/window_matcher.v
View file

@ -36,34 +36,37 @@ module window_matcher(
output [7:0] out_red, [7:0] out_green, [7:0] out_blue,
/* Overlay data IO */
output reg win_hsync, reg win_vsync,
output win_blank,
output reg win_blank,
output [11:0] win_x_dbg,
output [11:0] win_y_dbg,
output [11:0] win_w_dbg,
output [11:0] win_h_dbg,
output reg [11:0] win_w,
output reg [11:0] win_h,
output reg win_locked,
input [7:0] win_red, [7:0] win_green, [7:0] win_blue,
/* Extracted data output */
output out_data_en,
output reg out_data_en,
output reg out_data_valid,
output [23:0] out_data,
output [7:0] debug
);
assign win_blank = ~win_hsync;
wire [23:0] in_pxd = {in_red, in_green, in_blue};
wire [23:0] win_pxd = {win_red, win_green, win_blue};
wire [23:0] out_pxd;
assign {out_red, out_green, out_blue} = out_pxd;
assign debug = {in_pxd_match_dbg, win_blank, win_hactive, 2'b00};
/* Pattern matching */
localparam [23:0] MARKER_0 = 24'h012345;
localparam [23:0] MARKER_1 = 24'h6789ab;
localparam [23:0] MARKER_2 = 24'hcdef42;
localparam [23:0] MARKER_3 = 24'h543210;
wire [3:0] in_pxd_match = {
in_pxd == MARKER_3,
in_pxd == MARKER_2,
@ -84,15 +87,14 @@ module window_matcher(
end
end
assign debug = {in_pxd_match_dbg, win_hsync_int, win_vsync_int, 2'b00};
reg [3:0] in_pxd_match_sr [2:0];
wire in_pxd_pattern_match =
in_pxd_match[3] == 1
&& in_pxd_match_sr[2][0] == 1
&& in_pxd_match_sr[1][1] == 1
&& in_pxd_match_sr[0][2] == 1
&& in_blank == 0;
/* Window matching shift register */
&& !in_blank;
always @(posedge clk) begin
if (rst == 1) begin
in_pxd_match_sr[0] <= 0;
@ -104,126 +106,11 @@ module window_matcher(
in_pxd_match_sr[2] <= in_pxd_match_sr[1];
end
end
/* Window matching state machine */
reg [11:0] scan_x;
reg [11:0] scan_y;
reg [11:0] win_x_int;
reg [11:0] win_y_int;
reg [11:0] win_w_int;
reg [11:0] win_h_int;
reg win_hsync_int, win_vsync_int;
localparam ST_MAT_WAITING = 6'b000000,
ST_MAT_RX0 = 6'b000001,
ST_MAT_RX1 = 6'b000010,
ST_MAT_RX2 = 6'b000100,
ST_MAT_RX3 = 6'b001000,
ST_MAT_MATCHED = 6'b010000,
ST_MAT_DATA = 6'b100000;
reg [5:0] matcher_state;
wire matched = matcher_state[5];
/* Window sync generator */
reg [11:0] win_hsync_ctr_int;
reg [11:0] win_vsync_ctr_int;
always @(posedge clk) begin
if (rst == 1) begin
win_hsync_int <= 0;
win_vsync_int <= 0;
win_hsync_ctr_int <= 0;
win_vsync_ctr_int <= 0;
out_data_valid <= 0;
end
if (rst || in_vsync) begin
matcher_state <= ST_MAT_WAITING;
win_w_int <= 0;
win_h_int <= 0;
end
if (!rst) begin
if (in_blank) begin
/* Reset state if the header is only partially contained in this frame */
if (matcher_state != ST_MAT_DATA) begin
matcher_state <= ST_MAT_WAITING;
end
end else begin
case (matcher_state)
ST_MAT_WAITING: begin
if (in_pxd_pattern_match) begin
matcher_state <= ST_MAT_RX0;
win_x_int <= scan_x_reg[2];
win_y_int <= scan_y;
end
end
ST_MAT_RX0: begin
matcher_state <= ST_MAT_RX1;
end
ST_MAT_RX1: begin
matcher_state <= ST_MAT_RX2;
end
ST_MAT_RX2: begin
matcher_state <= ST_MAT_RX3;
win_w_int <= in_pxd;
end
ST_MAT_RX3: begin
matcher_state <= ST_MAT_MATCHED;
win_h_int <= in_pxd;
end
ST_MAT_MATCHED: begin
matcher_state <= ST_MAT_DATA;
win_hsync_int <= 1;
out_data_valid <= 1;
win_vsync_int <= 1;
win_hsync_ctr_int <= 9;
win_vsync_ctr_int <= 0;
end
endcase
end
if (matcher_state == ST_MAT_DATA) begin
/* hsync */
if (scan_x == win_x_int && win_vsync_int == 1) begin
win_hsync_int <= 1;
win_hsync_ctr_int <= 1;
out_data_valid <= 1;
end
if (win_hsync_int == 1) begin
win_hsync_ctr_int <= win_hsync_ctr_int + 1;
end
if (win_hsync_ctr_int == win_w_int || in_blank_reg == 0) begin
win_hsync_int <= 0;
out_data_valid <= 0;
win_hsync_ctr_int <= 0;
end
if (in_hsync_reg == 1 && in_hsync == 0) begin
if (scan_y == win_y_int) begin
win_vsync_int <= 1;
win_vsync_ctr_int <= 0;
end
win_vsync_ctr_int <= win_vsync_ctr_int + 1;
end
if (win_vsync_ctr_int == win_h_int) begin
win_vsync_int <= 0;
end
if (in_vsync_reg == 1 && in_vsync == 0) begin
win_vsync_ctr_int <= 0;
end
end
end
end
/* Pixel scan state machine */
reg [11:0] scan_x;
reg [11:0] scan_y;
reg [11:0] scan_x_reg [3:0];
reg in_hsync_reg;
reg in_vsync_reg;
@ -257,15 +144,12 @@ module window_matcher(
scan_x_reg[2] <= scan_x_reg[1];
scan_x_reg[3] <= scan_x_reg[2];
if (in_hsync == 1) begin
if (!in_blank) begin
scan_x <= scan_x + 1;
end
if (in_hsync_reg == 1 && in_hsync == 0) begin
if (!in_blank_reg && in_blank) begin
scan_y <= scan_y + 1;
end
if (in_hsync_reg == 0 && in_hsync == 1) begin
scan_x_reg[0] <= 0;
scan_x_reg[1] <= 0;
scan_x_reg[2] <= 0;
@ -273,19 +157,121 @@ module window_matcher(
scan_x <= 0;
end
if (in_vsync_reg == 1 && in_vsync == 0) begin
if (in_vsync_reg && !in_vsync) begin
scan_y <= 0;
end
end
end
/* Window matching state machine */
reg [11:0] win_x_int;
reg [11:0] win_y_int;
reg [11:0] win_w_int;
reg [11:0] win_h_int;
assign win_x_dbg = win_x_int;
assign win_y_dbg = win_y_int;
assign win_w_dbg = win_w_int;
assign win_h_dbg = win_h_int;
localparam ST_MAT_WAITING = 6'b000000,
ST_MAT_RX0 = 6'b000001,
ST_MAT_RX1 = 6'b000010,
ST_MAT_RX2 = 6'b000100,
ST_MAT_RX3 = 6'b001000,
ST_MAT_MATCHED = 6'b010000,
ST_MAT_DATA = 6'b100000;
reg [5:0] matcher_state;
wire matched = matcher_state[5];
reg [11:0] dval_x_reg;
reg [11:0] dval_y_reg;
always @(posedge clk) begin
if (rst == 1) begin
out_data_valid <= 0;
out_data_en <= 0;
end
if (rst || in_vsync) begin
matcher_state <= ST_MAT_WAITING;
win_x_int <= 0;
win_y_int <= 0;
win_w_int <= 0;
win_h_int <= 0;
end
if (!rst) begin
if (in_blank) begin
/* Reset state if the header is only partially contained in this frame */
if (matcher_state != ST_MAT_DATA) begin
matcher_state <= ST_MAT_WAITING;
end
end else begin
case (matcher_state)
ST_MAT_WAITING: begin
if (in_pxd_pattern_match) begin
matcher_state <= ST_MAT_RX0;
win_x_int <= scan_x_reg[3];
win_y_int <= scan_y;
end
end
ST_MAT_RX0: begin
matcher_state <= ST_MAT_RX1;
end
ST_MAT_RX1: begin
matcher_state <= ST_MAT_RX2;
end
ST_MAT_RX2: begin
matcher_state <= ST_MAT_RX3;
win_w_int <= in_pxd;
end
ST_MAT_RX3: begin
matcher_state <= ST_MAT_MATCHED;
win_h_int <= in_pxd;
end
ST_MAT_MATCHED: begin
matcher_state <= ST_MAT_DATA;
out_data_valid <= 1;
out_data_en <= 1;
dval_x_reg <= 9;
dval_y_reg <= 0;
end
endcase
end
if (matcher_state == ST_MAT_DATA) begin
/* blank */
if (scan_x == win_x_int && out_data_en) begin
out_data_valid <= 1;
dval_x_reg <= 1;
end
if (out_data_en) begin
dval_x_reg <= dval_x_reg + 1;
end
if (dval_x_reg == win_w_int || in_blank) begin
out_data_valid <= 0;
end
if (!in_blank_reg && in_blank) begin
dval_y_reg <= dval_y_reg + 1;
end
if (dval_y_reg == win_h_int) begin
out_data_en <= 0;
end
end
end
end
/* Match locking process */
reg [11:0] win_x;
reg [11:0] win_y;
reg match_locked; /* Goes high after a frame with a marker has been fully received */
always @(posedge clk) begin
if (rst) begin
match_locked <= 0;
win_locked <= 0;
win_w <= 0;
win_h <= 0;
@ -293,8 +279,7 @@ module window_matcher(
win_y <= 0;
end else begin
if (in_vsync_reg == 1 && in_vsync == 0) begin
match_locked <= matched;
if (in_vsync_reg == 0 && in_vsync == 1) begin
win_locked <= matched;
if (matched) begin
@ -314,48 +299,49 @@ module window_matcher(
/* Window H/VSYNC outputs */
reg [11:0] win_blank_ctr;
reg [11:0] win_hsync_ctr;
reg [11:0] win_vsync_ctr;
reg win_hactive;
always @(posedge clk) begin
if (rst == 1) begin
win_hsync <= 0;
win_vsync <= 0;
if (rst) begin
win_blank <= 1;
win_hactive <= 0;
win_blank_ctr <= 0;
win_hsync_ctr <= 0;
win_vsync_ctr <= 0;
end else begin
if (match_locked) begin
if (win_locked) begin
/* hsync */
if (scan_x == win_x && win_vsync == 1) begin
win_hsync <= 1;
win_hsync_ctr <= 1;
if (scan_x == win_x && win_hactive) begin
win_blank <= 0;
win_blank_ctr <= 1;
end
if (win_hsync == 1) begin
if (win_blank == 0) begin
win_blank_ctr <= win_blank_ctr + 1;
end
if (win_blank_ctr == win_w || in_blank) begin
win_blank <= 1;
win_blank_ctr <= 0;
end
if (win_hactive && in_blank_reg && !in_blank) begin
win_hsync_ctr <= win_hsync_ctr + 1;
end
if (win_hsync_ctr == win_w || in_hsync_reg == 0) begin
win_hsync <= 0;
win_hsync_ctr <= 0;
end
if (in_hsync_reg == 1 && in_hsync == 0 && win_vsync) begin
win_vsync_ctr <= win_vsync_ctr + 1;
end
if (scan_y == win_y) begin
win_vsync <= 1;
win_hactive <= 1;
end
if (win_vsync_ctr == win_h) begin
win_vsync <= 0;
if (win_hsync_ctr == win_h && !in_blank_reg && in_blank) begin
win_hactive <= 0;
end
if (in_vsync_reg == 1 && in_vsync == 0) begin
win_vsync_ctr <= 0;
win_vsync <= 0;
win_hsync_ctr <= 0;
win_hactive <= 0;
end
end
end
@ -365,9 +351,8 @@ module window_matcher(
reg [23:0] in_pxd_last;
always @(posedge clk) in_pxd_last <= rst ? 0 : in_pxd;
assign out_data_en = (matcher_state == ST_MAT_DATA);
assign out_data = out_data_en ? in_pxd_last : 0;
/* Compositor */
assign out_pxd = (win_hsync_int && !bypass) ? win_pxd : in_pxd_reg;
assign out_pxd = (!win_blank && !bypass) ? win_pxd : in_pxd_reg;
endmodule

15
test_bench/window_matcher_tb.v
View file

@ -25,16 +25,15 @@ module window_matcher_tb();
reg clk;
reg rst;
wire in_blank;
reg in_blank;
reg in_hsync;
reg in_vsync;
reg [7:0] in_red;
reg [7:0] in_green;
reg [7:0] in_blue;
wire win_hsync;
wire win_vsync;
wire win_blank;
wire win_hsync;
wire win_locked;
wire [11:0] win_w;
@ -45,12 +44,11 @@ module window_matcher_tb();
wire [23:0] out_data;
localparam period = 4;
assign in_blank = !(in_vsync && in_hsync);
initial begin
clk = 0;
rst = 1;
in_blank = 1;
in_hsync = 0;
in_vsync = 0;
in_red = 0;
@ -68,8 +66,9 @@ module window_matcher_tb();
reg [23:0] expected_data;
reg [23:0] expected_data_last;
integer testcase_id;
reg win_hsync_exp, win_vsync_exp, win_header;
reg win_hsync_exp_last, win_vsync_exp_last, win_header_last;
reg win_blank_exp, win_header;
reg win_blank_exp_last, win_header_last;
reg in_vsync_last;
initial begin
`include "test_data/00WM_TEST_POS_RUNNERS.v"
$finish;
@ -88,8 +87,6 @@ module window_matcher_tb();
.in_green(in_green),
.in_blue(in_blue),
.win_hsync(win_hsync),
.win_vsync(win_vsync),
.win_blank(win_blank),
.win_locked(win_locked),
.win_w(win_w),

307
test_bench/window_matcher_tb_gen.ipynb
View file

File diff suppressed because one or more lines are too long

71
window_matcher_tb_behav.wcfg
View file

@ -11,15 +11,15 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="5693629750fs"></ZoomStartTime>
<ZoomEndTime time="5694933251fs"></ZoomEndTime>
<ZoomStartTime time="5694498416fs"></ZoomStartTime>
<ZoomEndTime time="5694759517fs"></ZoomEndTime>
<Cursor1Time time="5694716000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="175"></NameColumnWidth>
<ValueColumnWidth column_width="166"></ValueColumnWidth>
<ValueColumnWidth column_width="162"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="54" />
<WVObjectSize size="48" />
<wvobject fp_name="/window_matcher_tb/window_matcher_i/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
@ -68,41 +68,25 @@
<obj_property name="ElementShortName">out_green[7:0]</obj_property>
<obj_property name="ObjectShortName">out_green[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_hsync" type="logic">
<obj_property name="ElementShortName">win_hsync</obj_property>
<obj_property name="ObjectShortName">win_hsync</obj_property>
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<wvobject fp_name="/window_matcher_tb/win_blank" type="logic">
<obj_property name="ElementShortName">win_blank</obj_property>
<obj_property name="ObjectShortName">win_blank</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_hactive" type="logic">
<obj_property name="ElementShortName">win_hactive</obj_property>
<obj_property name="ObjectShortName">win_hactive</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/win_locked" type="logic">
<obj_property name="ElementShortName">win_locked</obj_property>
<obj_property name="ObjectShortName">win_locked</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/out_blue" type="array">
<obj_property name="ElementShortName">out_blue[7:0]</obj_property>
<obj_property name="ObjectShortName">out_blue[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_hsync_int" type="logic">
<obj_property name="ElementShortName">win_hsync_int</obj_property>
<obj_property name="ObjectShortName">win_hsync_int</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/win_hsync_exp" type="logic">
<obj_property name="ElementShortName">win_hsync_exp</obj_property>
<obj_property name="ObjectShortName">win_hsync_exp</obj_property>
<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_vsync" type="logic">
<obj_property name="ElementShortName">win_vsync</obj_property>
<obj_property name="ObjectShortName">win_vsync</obj_property>
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_vsync_int" type="logic">
<obj_property name="ElementShortName">win_vsync_int</obj_property>
<obj_property name="ObjectShortName">win_vsync_int</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/win_vsync_exp" type="logic">
<obj_property name="ElementShortName">win_vsync_exp</obj_property>
<obj_property name="ObjectShortName">win_vsync_exp</obj_property>
<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<wvobject fp_name="/window_matcher_tb/win_blank_exp" type="logic">
<obj_property name="ElementShortName">win_blank_exp</obj_property>
<obj_property name="ObjectShortName">win_blank_exp</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/out_data_en" type="logic">
<obj_property name="ElementShortName">out_data_en</obj_property>
@ -201,21 +185,6 @@
<obj_property name="ObjectShortName">win_hsync_ctr[11:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_hsync_ctr_int" type="array">
<obj_property name="ElementShortName">win_hsync_ctr_int[11:0]</obj_property>
<obj_property name="ObjectShortName">win_hsync_ctr_int[11:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_vsync_ctr" type="array">
<obj_property name="ElementShortName">win_vsync_ctr[11:0]</obj_property>
<obj_property name="ObjectShortName">win_vsync_ctr[11:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/win_vsync_ctr_int" type="array">
<obj_property name="ElementShortName">win_vsync_ctr_int[11:0]</obj_property>
<obj_property name="ObjectShortName">win_vsync_ctr_int[11:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/matcher_state" type="array">
<obj_property name="ElementShortName">matcher_state[5:0]</obj_property>
<obj_property name="ObjectShortName">matcher_state[5:0]</obj_property>
@ -240,10 +209,6 @@
<obj_property name="ElementShortName">in_pxd_reg[23:0]</obj_property>
<obj_property name="ObjectShortName">in_pxd_reg[23:0]</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/window_matcher_i/match_locked" type="logic">
<obj_property name="ElementShortName">match_locked</obj_property>
<obj_property name="ObjectShortName">match_locked</obj_property>
</wvobject>
<wvobject fp_name="/window_matcher_tb/testcase_id" type="array">
<obj_property name="ElementShortName">testcase_id[31:0]</obj_property>
<obj_property name="ObjectShortName">testcase_id[31:0]</obj_property>