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Added code that allows the raw HDMI data to be logged to the serial port.

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Also fixed issue that was causing a run pulse on the VSYNC signal, that was confusing the modules that overlayed data
This commit is contained in:
Mike Field 2015-08-08 22:13:26 +12:00
parent 66d6b029c8
commit 26a416de67
13 changed files with 326 additions and 49 deletions
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18
Artix-7-HDMI-processing.xpr
View file

@ -19,13 +19,13 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/src/tmds_decoder.vhd">
<File Path="$PPRDIR/src/deserialiser_1_to_10.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/src/deserialiser_1_to_10.vhd">
<File Path="$PPRDIR/src/tmds_decoder.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@ -55,6 +55,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/src/guidelines.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/src/audio_to_db.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -115,7 +121,7 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/src/guidelines.vhd">
<File Path="$PPRDIR/src/symbol_dump.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@ -210,12 +216,18 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_hdmi_decode_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_hdmi_decode"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_hdmi_decode_behav.wcfg"/>
</Config>
</FileSet>
</FileSets>

5
constraints/NexysVideo.xdc
View file

@ -66,4 +66,7 @@ set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { led[3]
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { led[5] }]; #IO_L16N_T2_13 Sch=led[5]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { led[6] }]; #IO_L16P_T2_13 Sch=led[6]
set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]
set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]
##UART
set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { rs232_tx }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out

2
src/conversion_to_RGB.vhd
View file

@ -197,7 +197,7 @@ clk_proc: process(clk)
s2_W <= s1_W;
end if;
R_raw <= a + d - to_unsigned(4767*256 + 0*2048 + 7344*2048, 27);
G_raw <= a - b - e - to_unsigned(4767*256 - 872*2048 - 2183*2048, 27);
G_raw <= a - b - e + to_unsigned(-4767*256 + 872*2048 + 2183*2048, 27);
B_raw <= a + c - to_unsigned(4767*256 + 8650*2048 + 0*2048, 27);
-------------------------------------------------

47
src/hdmi_design.vhd
View file

@ -79,7 +79,9 @@ entity hdmi_design is
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0)
hdmi_tx_n : out std_logic_vector(2 downto 0);
-- For dumping symbols
rs232_tx : out std_logic
);
end hdmi_design;
@ -147,9 +149,20 @@ architecture Behavioral of hdmi_design is
out_vsync : in std_logic;
out_red : in std_logic_vector(7 downto 0);
out_green : in std_logic_vector(7 downto 0);
out_blue : in std_logic_vector(7 downto 0)
out_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
symbol_sync : out std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end component;
signal symbol_sync : std_logic;
signal symbol_ch0 : std_logic_vector(9 downto 0);
signal symbol_ch1 : std_logic_vector(9 downto 0);
signal symbol_ch2 : std_logic_vector(9 downto 0);
component pixel_processing is
Port ( clk : in STD_LOGIC;
@ -185,6 +198,17 @@ architecture Behavioral of hdmi_design is
);
end component;
component symbol_dump is
port (
clk : in std_logic;
clk100 : in std_logic;
symbol_sync : in std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : in std_logic_vector(9 downto 0);
symbol_ch1 : in std_logic_vector(9 downto 0);
symbol_ch2 : in std_logic_vector(9 downto 0);
rs232_tx : out std_logic);
end component;
signal pixel_clk : std_logic;
signal in_blank : std_logic;
signal in_hsync : std_logic;
@ -255,6 +279,9 @@ i_hdmi_io: hdmi_io port map (
in_green => in_green,
in_blue => in_blue,
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
audio_channel => audio_channel,
audio_de => audio_de,
audio_sample => audio_sample,
@ -267,7 +294,12 @@ i_hdmi_io: hdmi_io port map (
out_vsync => out_vsync,
out_red => out_red,
out_green => out_green,
out_blue => out_blue
out_blue => out_blue,
symbol_sync => symbol_sync,
symbol_ch0 => symbol_ch0,
symbol_ch1 => symbol_ch1,
symbol_ch2 => symbol_ch2
);
i_processing: pixel_processing Port map (
@ -298,4 +330,13 @@ i_processing: pixel_processing Port map (
out_blue => out_blue
);
i_symbol_dump: symbol_dump port map (
clk => pixel_clk,
clk100 => clk100,
symbol_sync => symbol_sync,
symbol_ch0 => symbol_ch0,
symbol_ch1 => symbol_ch1,
symbol_ch2 => symbol_ch2,
rs232_tx => rs232_tx);
end Behavioral;

43
src/hdmi_input.vhd
View file

@ -86,7 +86,12 @@ entity hdmi_input is
adp_subpacket0_bits : out std_logic_vector(1 downto 0);
adp_subpacket1_bits : out std_logic_vector(1 downto 0);
adp_subpacket2_bits : out std_logic_vector(1 downto 0);
adp_subpacket3_bits : out std_logic_vector(1 downto 0)
adp_subpacket3_bits : out std_logic_vector(1 downto 0);
-- For later reuse
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end hdmi_input;
@ -101,6 +106,7 @@ architecture Behavioral of hdmi_input is
reset : in STD_LOGIC;
ce : in STD_LOGIC;
invalid_symbol : out std_logic;
symbol : out std_logic_vector (9 downto 0);
ctl_valid : out std_logic;
ctl : out std_logic_vector (1 downto 0);
terc4_valid : out std_logic;
@ -113,32 +119,6 @@ architecture Behavioral of hdmi_input is
end component;
signal clk_pixel_raw : std_logic;
component deserialiser_1_to_10 is
Port ( clk_mgmt : in std_logic;
delay_ce : in std_logic;
delay_count : in std_logic_vector (4 downto 0);
clk : in std_logic;
clk_x1 : in std_logic;
bitslip : in std_logic;
clk_x5 : in std_logic;
reset : in std_logic;
serial : in std_logic;
data : out std_logic_vector (9 downto 0));
end component;
component TMDS_decoder is
Port ( clk : in std_logic;
symbol : in std_logic_vector (9 downto 0);
invalid_symbol : out std_logic;
ctl_valid : out std_logic;
ctl : out std_logic_vector (1 downto 0);
terc4_valid : out std_logic;
terc4 : out std_logic_vector (3 downto 0);
guardband_valid : out std_logic;
guardband : out std_logic_vector (0 downto 0);
data_valid : out std_logic;
data : out std_logic_vector (7 downto 0));
end component;
component alingment_detect is
Port ( clk : in STD_LOGIC;
@ -259,6 +239,10 @@ begin
pll_locked <= locked;
symbol_sync <= symbol_sync_i;
reset <= std_logic(reset_counter(reset_counter'high));
symbol_ch0 <= ch0_symbol;
symbol_ch1 <= ch1_symbol;
symbol_ch2 <= ch2_symbol;
debug <= ch2_invalid_symbol & ch1_invalid_symbol & ch0_invalid_symbol & dvid_mode & locked & symbol_sync_i;
@ -443,6 +427,7 @@ ch0: input_channel Port map (
clk_x5 => clk_pixel_x5,
serial => hdmi_in_ch0,
invalid_symbol => ch0_invalid_symbol,
symbol => ch0_symbol,
ctl_valid => ch0_ctl_valid,
ctl => ch0_ctl,
terc4_valid => ch0_terc4_valid,
@ -461,6 +446,7 @@ ch1: input_channel Port map (
clk_x1 => clk_pixel_x1,
clk_x5 => clk_pixel_x5,
serial => hdmi_in_ch1,
symbol => ch1_symbol,
invalid_symbol => ch1_invalid_symbol,
ctl_valid => ch1_ctl_valid,
ctl => ch1_ctl,
@ -481,6 +467,7 @@ ch2: input_channel Port map (
clk_x5 => clk_pixel_x5,
serial => hdmi_in_ch2,
invalid_symbol => ch2_invalid_symbol,
symbol => ch2_symbol,
ctl_valid => ch2_ctl_valid,
ctl => ch2_ctl,
terc4_valid => ch2_terc4_valid,
@ -597,7 +584,7 @@ hdmi_section_decode: process(clk_pixel)
-- encoded in TERC4 coded in Ch0 - annoying!
---------------------------------------------
adp_guardband_detect <= '0';
if ch0_terc4_valid = '1' and ch1_guardband_valid = '1' and ch1_guardband_valid = '1' then
if in_vdp = '0' and ch0_terc4_valid = '1' and ch1_guardband_valid = '1' and ch1_guardband_valid = '1' then
if ch0_terc4(3 downto 2) = "11" and ch1_guardband = "0" and ch2_guardband = "0" then
raw_vsync <= ch0_terc4(1);
raw_hsync <= ch0_terc4(0);

37
src/hdmi_io.vhd
View file

@ -112,7 +112,15 @@ entity hdmi_io is
-------------------------------------
audio_channel : out std_logic_vector(2 downto 0);
audio_de : out std_logic;
audio_sample : out std_logic_vector(23 downto 0)
audio_sample : out std_logic_vector(23 downto 0);
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
symbol_sync : out std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end entity;
@ -159,7 +167,12 @@ architecture Behavioral of hdmi_io is
adp_subpacket0_bits : out std_logic_vector(1 downto 0);
adp_subpacket1_bits : out std_logic_vector(1 downto 0);
adp_subpacket2_bits : out std_logic_vector(1 downto 0);
adp_subpacket3_bits : out std_logic_vector(1 downto 0)
adp_subpacket3_bits : out std_logic_vector(1 downto 0);
-- For later reuse
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end component;
@ -330,6 +343,7 @@ architecture Behavioral of hdmi_io is
signal tmds_out_ch1 : std_logic;
signal tmds_out_ch2 : std_logic;
signal detect_sr : std_logic_vector(7 downto 0) := (others => '0');
begin
pixel_clk <= pixel_clk_i;
hdmi_rx_hpa <= '1';
@ -393,7 +407,11 @@ i_hdmi_input : hdmi_input port map (
adp_subpacket0_bits => adp_subpacket0_bits,
adp_subpacket1_bits => adp_subpacket1_bits,
adp_subpacket2_bits => adp_subpacket2_bits,
adp_subpacket3_bits => adp_subpacket3_bits
adp_subpacket3_bits => adp_subpacket3_bits,
-- For later reuse
symbol_ch0 => symbol_ch0,
symbol_ch1 => symbol_ch1,
symbol_ch2 => symbol_ch2
);
-------------------------------------
@ -550,4 +568,17 @@ out_tx1_buf: OBUFDS generic map ( IOSTANDARD => "TMDS_33", SLEW => "FAST")
out_tx2_buf: OBUFDS generic map ( IOSTANDARD => "TMDS_33", SLEW => "FAST")
port map ( O => hdmi_tx_p(2), OB => hdmi_tx_n(2), I => tmds_out_ch2);
-- Detect when VSYNC is held high for 8 cycles, so we can synchronise the capture of symbols
process(pixel_clk_i)
begin
if rising_edge(pixel_clk_i) then
if detect_sr = "11111111" and raw_vsync = '0' then
symbol_sync <= '1';
else
symbol_sync <= '0';
end if;
detect_sr <= detect_sr(6 downto 0) & raw_vsync;
end if;
end process;
end Behavioral;

8
src/input_channel.vhd
View file

@ -57,6 +57,7 @@ entity input_channel is
reset : in std_logic;
ce : in STD_LOGIC;
invalid_symbol : out std_logic;
symbol : out std_logic_vector (9 downto 0);
ctl_valid : out std_logic;
ctl : out std_logic_vector (1 downto 0);
terc4_valid : out std_logic;
@ -110,10 +111,11 @@ architecture Behavioral of input_channel is
signal delay_ce : STD_LOGIC;
signal bitslip : STD_LOGIC;
signal symbol_sync_i : STD_LOGIC;
signal symbol : std_logic_vector (9 downto 0);
signal symbol_i : std_logic_vector (9 downto 0);
signal invalid_symbol_i: STD_LOGIC;
begin
symbol <= symbol_i;
i_deser: deserialiser_1_to_10 port map (
clk_mgmt => clk_mgmt,
@ -126,11 +128,11 @@ i_deser: deserialiser_1_to_10 port map (
clk_x5 => clk_x5,
reset => reset,
serial => serial,
data => symbol);
data => symbol_i);
i_decoder: tmds_decoder port map (
clk => clk,
symbol => symbol,
symbol => symbol_i,
invalid_symbol => invalid_symbol_i,
ctl_valid => ctl_valid,
ctl => ctl,

192
src/symbol_dump.vhd Normal file
View file

@ -0,0 +1,192 @@
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: symbol_dump - Behavioral
--
-- Description: Create a trace of HDMI symbols - a 1024 word memory block is filled
-- and then transmitted over rs232. Then refilled again, but this time
-- waiting an extra 1024 cycles from when symbol_sync is asserted.
--
-- If the video source is paused, then the entire frame can be capbured
-- (excluding ADP data periods, which might get broken on the boundary.
--
-- The captured data can then be analysed by hand or used to drive
-- simulations.
--
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - with the industry metric of 30 lines
-- per day, it is equivalent to about 6 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design how about trying PayPal?
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity symbol_dump is
Port ( clk : in STD_LOGIC;
clk100 : in STD_LOGIC;
symbol_sync : in STD_LOGIC;
symbol_ch0 : in STD_LOGIC_VECTOR (9 downto 0);
symbol_ch1 : in STD_LOGIC_VECTOR (9 downto 0);
symbol_ch2 : in STD_LOGIC_VECTOR (9 downto 0);
rs232_tx : out STD_LOGIC);
end symbol_dump;
architecture Behavioral of symbol_dump is
type array_hex is array(0 to 15) of std_logic_vector(9 downto 0);
signal hex : array_hex := (
"1001100000", "1001100010", "1001100100", "1001100110",
"1001101000", "1001101010", "1001101100", "1001101110",
"1001110000", "1001110010", "1010000010", "1010000100",
"1010000110", "1010001000", "1010001010", "1010001100");
type array_memory is array(0 to 1023) of std_logic_vector(29 downto 0);
signal memory : array_memory := (others => (others =>'0'));
signal position : unsigned(23 downto 0) := (others => '0');
signal capture_point : unsigned(23 downto 0) := (others => '0');
signal write_address : unsigned(9 downto 0) := (others => '0');
signal write_enable : std_logic := '0';
signal write_data : std_logic_vector(29 downto 0) := (others => '0');
--- For signaling into the 100MHz domain
signal ready_to_send : std_logic := '0';
signal ready_to_send_meta : std_logic := '0';
signal ready_to_send_synced : std_logic := '0';
--- For signaling into the pixel clock domain
signal sending_data : std_logic := '0';
signal sending_data_meta : std_logic := '0';
signal sending_data_synced : std_logic := '0';
signal rd_address : unsigned(9 downto 0) := (others => '0');
signal rd_data : std_logic_vector(29 downto 0) := (others => '0');
signal tx_data : std_logic_vector(89 downto 0) := (others => '1');
signal tx_count : unsigned(7 downto 0) := (others => '0');
signal baud_counter : unsigned(12 downto 0) := (others => '0');
signal baud_counter_max : unsigned(12 downto 0) := to_unsigned(100000000/115200,13);
begin
process(clk)
begin
if rising_edge(clk) then
if write_enable = '1' then
memory(to_integer(write_address)) <= symbol_ch2 & symbol_ch1 & symbol_ch0;
end if;
-- track where we are in the frame.
if symbol_sync = '1' then
position <= (others => '0');
else
position <= position+1;
end if;
-- If we are capturing remember where we have got up to
-- and see if we have captured our full amount.
if write_enable = '1' then
capture_point <= position;
write_data <= symbol_ch2 & symbol_ch1 & symbol_ch0;
write_data <= symbol_ch2 & symbol_ch1 & symbol_ch0;
if write_address = 1023 then
write_enable <= '0';
ready_to_send <= '1';
end if;
write_address <= write_address+1;
end if;
-- Do we start capturing at this point?
-- (write address resets itself to 0, so we don't
-- have to do it here)
if position = capture_point and ready_to_send = '0' and sending_data_synced = '0' then
write_enable <= '1';
end if;
-- Do we need to re-arm ready for the next capture
if sending_data_synced = '1' then
ready_to_send <= '0';
end if;
-- Bring data_sent into this clock domain
sending_data_synced <= sending_data_meta;
sending_data_meta <= sending_data;
end if;
end process;
process(clk100)
begin
if rising_edge(clk100) then
if baud_counter = 0 then
rs232_tx <= tx_data(0);
tx_data <= '1' & tx_data(89 downto 1);
baud_counter <= baud_counter_max;
if(tx_count > 0) then
tx_count <= tx_count-1;
end if;
else
baud_counter <= baud_counter -1;
end if;
if sending_data = '1' or ready_to_send_synced = '1' then
if tx_count = 0 then
tx_data(89 downto 80) <= hex(to_integer(unsigned(rd_data( 3 downto 0))));
tx_data(79 downto 70) <= hex(to_integer(unsigned(rd_data( 7 downto 4))));
tx_data(69 downto 60) <= hex(to_integer(unsigned(rd_data(11 downto 8))));
tx_data(59 downto 50) <= hex(to_integer(unsigned(rd_data(15 downto 12))));
tx_data(49 downto 40) <= hex(to_integer(unsigned(rd_data(19 downto 16))));
tx_data(39 downto 30) <= hex(to_integer(unsigned(rd_data(23 downto 20))));
tx_data(29 downto 20) <= hex(to_integer(unsigned(rd_data(27 downto 24))));
tx_data(19 downto 10) <= hex(to_integer(unsigned(rd_data(29 downto 28))));
tx_data( 9 downto 0) <= "1000010100"; -- New line
tx_count <= to_unsigned(90,8);
rd_data <= memory(to_integer(rd_address));
rd_address <= rd_address+1;
if rd_address = 1023 then
sending_data <= '0';
else
sending_data <= '1';
end if;
end if;
end if;
-- Bring the ready to send signal into this clock domain
ready_to_send_synced <= ready_to_send_meta;
ready_to_send_meta <= ready_to_send;
end if;
end process;
end Behavioral;

3
test_bench/hdmi_test_generator/hdmi_ouput_test.vhd
View file

@ -40,7 +40,8 @@
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--
----------------------------------------------------------------------------------library IEEE;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hdmi_output_test is

3
test_bench/hdmi_test_generator/minimal_hdmi_symbols.vhd
View file

@ -41,7 +41,8 @@
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--
----------------------------------------------------------------------------------library IEEE;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

3
test_bench/hdmi_test_generator/vga_clocking.vhd
View file

@ -40,7 +40,8 @@
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--
----------------------------------------------------------------------------------library IEEE;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

3
test_bench/hdmi_test_generator/vga_gen.vhd
View file

@ -40,7 +40,8 @@
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--
----------------------------------------------------------------------------------library IEEE;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

11
test_bench/tb_hdmi_decode.vhd
View file

@ -55,7 +55,7 @@ architecture Behavioral of tb_hdmi_decode is
clk100 : in STD_LOGIC;
-- Control signals
led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(2 downto 0) :=(others => '0');
sw : in std_logic_vector(7 downto 0) :=(others => '0');
debug_pmod : out std_logic_vector(7 downto 0) :=(others => '0');
--HDMI input signals
@ -77,7 +77,9 @@ architecture Behavioral of tb_hdmi_decode is
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0)
hdmi_tx_n : out std_logic_vector(2 downto 0);
-- For dumping symbols
rs232_tx : out std_logic
);
end component;
@ -117,6 +119,7 @@ architecture Behavioral of tb_hdmi_decode is
signal hdmi_tx_n : std_logic_vector(2 downto 0);
signal sdat_drive : std_logic := '1';
signal rs232_tx : std_logic := '1';
begin
hdmi_rx_sda <= '0' when sdat_drive = '0' else 'H';
@ -173,7 +176,9 @@ uut: hdmi_design Port map (
hdmi_tx_rscl => hdmi_tx_rscl,
hdmi_tx_rsda => hdmi_tx_rsda,
hdmi_tx_p => hdmi_tx_p,
hdmi_tx_n => hdmi_tx_n
hdmi_tx_n => hdmi_tx_n,
rs232_tx => rs232_tx
);
edid_test_proc: process