jaseg
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8e1bf42f39
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Some small fixes, add silk artwork
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2018-11-29 10:18:56 +09:00 |
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jaseg
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9e50656e35
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pcb: Add BOM
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2018-11-27 17:14:46 +09:00 |
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jaseg
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ad86b13649
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pcb: Add project info to silk and do gerber export
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2018-11-27 11:37:35 +09:00 |
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jaseg
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2de3660f50
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PCB silk: hide testpoint references
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2018-11-22 10:21:26 +09:00 |
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jaseg
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47f48bea90
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Further PCB cleanup, initial silk cleanup
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2018-11-22 10:17:35 +09:00 |
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jaseg
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07ae18740e
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Some cleanups
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2018-11-21 23:05:42 +09:00 |
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jaseg
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bd93c5e229
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Initial PCB draft
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2018-11-21 22:18:37 +09:00 |
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jaseg
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f07540c367
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Add old architecture documents
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2018-11-19 21:22:44 +09:00 |
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jaseg
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194bd7fdb9
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Initial schematic commit
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2018-11-17 11:35:25 +09:00 |
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jaseg
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155a29ce08
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Boot, UART working
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2017-07-31 16:39:37 +02:00 |
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jaseg
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6482cf2a69
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USB HID host code import
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2017-07-30 16:10:36 +02:00 |
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jaseg
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b9535e1b08
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Initial commit, blink working
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2017-07-30 15:36:45 +02:00 |
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