90ce052d82
Doesn't do much other than reply with an increasing pattern, but at least the basic wiring is now in place.
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
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* March 2017 Karl Palsson <karlp@tweak.net.au>
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/rcc.h>
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#include "trace.h"
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#include "hw.h"
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struct hw_detail hw_details = {
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.periph = SPI2,
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.periph_rcc = RCC_SPI2,
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.periph_rst = RST_SPI2,
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.pins = GPIO13| GPIO14 | GPIO15, /* SPI pins for setting AF with */
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.port = GPIOB,
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.port_rcc = RCC_GPIOB,
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.trigger_rcc = RCC_GPIOB,
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.trigger_port = GPIOB,
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.trigger_pin = GPIO9,
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};
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/* provided in board files please*/
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/**
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* Setup any gpios or anything hardware specific.
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* Should _only_ be things that can't be done in shared init()
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*/
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static void hw_init(void)
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{
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/* trigger pin gpio */
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rcc_periph_clock_enable(hw_details.trigger_rcc);
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gpio_mode_setup(hw_details.trigger_port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, hw_details.trigger_pin);
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/* spi control lines */
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rcc_periph_clock_enable(hw_details.port_rcc);
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gpio_mode_setup(hw_details.port, GPIO_MODE_AF, GPIO_PUPD_NONE, hw_details.pins);
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gpio_set_output_options(hw_details.port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, hw_details.pins);
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gpio_set_af(hw_details.port, GPIO_AF5, hw_details.pins);
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}
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static void test_init(void)
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{
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/* Setup SPI parameters. */
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rcc_periph_clock_enable(hw_details.periph_rcc);
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/* mostly, this is just "write 0 to cr1" */
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spi_set_slave_mode(hw_details.periph);
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spi_send_msb_first(hw_details.periph);
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spi_set_dff_8bit(hw_details.periph);
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spi_set_clock_phase_0(hw_details.periph);
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spi_set_clock_polarity_0(hw_details.periph);
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spi_set_frf_motorola(hw_details.periph);
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/* we're a spi slave, use a CS pin */
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spi_disable_software_slave_management(hw_details.periph);
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SPI_CR2(hw_details.periph) &= ~SPI_CR2_SSOE;
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/* Finally enable the SPI. */
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spi_enable(hw_details.periph);
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}
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static void test_task(void) {
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static int i = 0;
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uint32_t spi = hw_details.periph;
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if (SPI_SR(spi) & SPI_SR_TXE) {
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/* ready to load next data in */
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SPI_DR(spi) = i++;
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}
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if (SPI_SR(spi) & SPI_SR_RXNE) {
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uint8_t data = SPI_DR(spi);
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trace_send8(2, data);
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}
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}
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static void setup(void)
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{
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printf("hi guys!\n");
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hw_init();
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test_init();
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}
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int main(void)
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{
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const struct rcc_clock_scale myclock = {
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.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
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.pll_mul = RCC_CFGR_PLLMUL_MUL4,
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.pll_div = RCC_CFGR_PLLDIV_DIV2,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_waitstates = 1,
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.ahb_frequency = 32e6,
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.apb1_frequency = 32e6,
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.apb2_frequency = 32e6,
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};
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int i, j;
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rcc_clock_setup_pll(&myclock);
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setup();
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while (1) {
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test_task();
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}
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return 0;
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}
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