136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
/*
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* Oct 2017 Karl Palsson <karlp@tweak.net.au>
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/flash.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/usart.h>
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#include "uart-basic.h"
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/* f3 pll setup, based on l1/f4*/
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typedef struct {
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uint8_t pll_mul;
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uint8_t pll_div;
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uint8_t pll_source;
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uint32_t flash_config;
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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uint32_t apb1_frequency;
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uint32_t apb2_frequency;
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uint32_t ahb_frequency;
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} rcc_clock_scale_t;
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static void rcc_clock_setup_pll_f3_special(const rcc_clock_scale_t *clock)
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{
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/* Turn on the appropriate source for the PLL */
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// TODO, some f3's have extra bits here
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enum rcc_osc my_osc;
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if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_PREDIV) {
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my_osc = RCC_HSE;
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} else {
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my_osc = RCC_HSI;
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}
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rcc_osc_on(my_osc);
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while (!rcc_is_osc_ready(my_osc));
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/* Configure flash settings. */
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flash_set_ws(clock->flash_config);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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rcc_osc_off(RCC_PLL);
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while (rcc_is_osc_ready(RCC_PLL));
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rcc_set_pll_source(clock->pll_source);
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rcc_set_pll_multiplier(clock->pll_mul);
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// TODO - iff pll_div != 0, then maybe we're on a target that
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// has the dividers?
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(RCC_PLL);
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while (!rcc_is_osc_ready(RCC_PLL));
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
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rcc_wait_for_sysclk_status(RCC_PLL);
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/* Set the peripheral clock frequencies used. */
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rcc_ahb_frequency = clock->ahb_frequency;
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rcc_apb1_frequency = clock->apb1_frequency;
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rcc_apb2_frequency = clock->apb2_frequency;
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}
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static void setup_clocks(void)
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{
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rcc_clock_scale_t clock_full_hse8mhz ={
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.pll_mul = RCC_CFGR_PLLMUL_PLL_IN_CLK_X9,
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.pll_source = RCC_CFGR_PLLSRC_HSE_PREDIV,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS,
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.apb1_frequency = 36000000,
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.apb2_frequency = 72000000,
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.ahb_frequency = 72000000,
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};
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rcc_clock_setup_pll_f3_special(&clock_full_hse8mhz);
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}
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void usart2_exti26_isr(void)
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{
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ub_irq_handler();
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}
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int main(void)
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{
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int i;
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int j = 0;
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setup_clocks();
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/* Board led */
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rcc_periph_clock_enable(RCC_GPIOE);
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gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO8);
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gpio_set(GPIOE, GPIO8);
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/* board init for uart2 on pa2/3 */
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rcc_periph_clock_enable(RCC_GPIOA);
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2|GPIO3);
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/* usart is AF7 */
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gpio_set_af(GPIOA, GPIO_AF7, GPIO2|GPIO3);
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struct ub_hw ub = {
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.uart = USART2,
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.uart_nvic = NVIC_USART2_EXTI26_IRQ,
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.uart_rcc = RCC_USART2,
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};
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ub_init(&ub);
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printf("hi guys!\n");
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while (1) {
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gpio_toggle(GPIOE, GPIO8);
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for (i = 0; i < 0x100000; i++) { /* Wait a bit. */
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__asm__("NOP");
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}
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ub_task();
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gpio_toggle(GPIOE, GPIO8);
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for (i = 0; i < 0x100000; i++) { /* Wait a bit. */
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__asm__("NOP");
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}
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}
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return 0;
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}
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