jaseg/olsndot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

fnord23

Browse source
This commit is contained in:
Matthias Hannig 2018-03-06 22:22:45 +01:00
parent f40a69915f
commit 6aaaa0b4ae
6 changed files with 18 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

BIN
firmware/.Makefile.swp Normal file
View file

Binary file not shown.

2
firmware/.gitignore vendored
View file

@ -10,4 +10,4 @@ sources.c
sources.tar.xz sources.tar.xz
sources.tar.xz.zip sources.tar.xz.zip
STM32Cube STM32Cube*

2
firmware/Makefile
View file

@ -32,7 +32,7 @@ cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/c
python3 gen_cmsis_exports.py $^ > $@ python3 gen_cmsis_exports.py $^ > $@
sources.tar.xz: main.c Makefile sources.tar.xz: main.c Makefile
tar -caf $@ $^ tar -cf $@ $^
# don't ask... # don't ask...
sources.tar.xz.zip: sources.tar.xz sources.tar.xz.zip: sources.tar.xz

4
firmware/main.c
View file

@ -53,7 +53,9 @@ void do_transpose(void);
* |<----------------NBITS---------------->| |<>|--ignored * |<----------------NBITS---------------->| |<>|--ignored
* | (MSB) brightness data (LSB) | |<>|--ignored * | (MSB) brightness data (LSB) | |<>|--ignored
*/ */
uint32_t brightness[32] = { 0 }; uint32_t brightness[32] = {
0x2222, 0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222
};
/* Bit-golfed modulation data generated from the above values by the main loop, ready to be sent out to the shift /* Bit-golfed modulation data generated from the above values by the main loop, ready to be sent out to the shift
* registers. * registers.

4
firmware/openocd.cfg
View file

@ -5,6 +5,8 @@ interface jlink
#adapter_khz 10000 #adapter_khz 10000
transport select swd transport select swd
source /usr/share/openocd/scripts/target/stm32f0x.cfg # source /usr/share/openocd/scripts/target/stm32f0x.cfg
# source [find interface/jlink.cfg]
source [find target/stm32f0x.cfg]
#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME #flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME

10
firmware/openocd_jaseg.cfg Normal file
View file

@ -0,0 +1,10 @@
telnet_port 4444
gdb_port 3333
interface jlink
#adapter_khz 10000
transport select swd
source /usr/share/openocd/scripts/target/stm32f0x.cfg
#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME