fnord23

firmware/.gitignore

@@ -10,4 +10,4 @@ sources.c
 sources.tar.xz
 sources.tar.xz.zip
 
-STM32Cube
+STM32Cube*

firmware/Makefile

@@ -32,7 +32,7 @@ cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/c
 	python3 gen_cmsis_exports.py $^ > $@
 
 sources.tar.xz: main.c Makefile
-	tar -caf $@ $^
+	tar -cf $@ $^
 
 # don't ask...
 sources.tar.xz.zip: sources.tar.xz

firmware/main.c

@@ -53,7 +53,9 @@ void do_transpose(void);
  *                                 |<----------------NBITS---------------->|  |<>|--ignored
  *                                 | (MSB)      brightness data      (LSB) |  |<>|--ignored
  */
-uint32_t brightness[32] = { 0 };
+uint32_t brightness[32] = {
+    0x2222, 0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222,0x2222
+};
 
 /* Bit-golfed modulation data generated from the above values by the main loop, ready to be sent out to the shift
  * registers.

firmware/openocd.cfg

@@ -5,6 +5,8 @@ interface jlink
 #adapter_khz 10000
 transport select swd
 
-source /usr/share/openocd/scripts/target/stm32f0x.cfg
+# source /usr/share/openocd/scripts/target/stm32f0x.cfg
+# source [find interface/jlink.cfg]
+source [find target/stm32f0x.cfg]
 
 #flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME

firmware/openocd_jaseg.cfg

@@ -0,0 +1,10 @@
+telnet_port 4444
+gdb_port 3333
+
+interface jlink
+#adapter_khz 10000
+transport select swd
+
+source /usr/share/openocd/scripts/target/stm32f0x.cfg
+
+#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME