Somewhat more linear slide
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4 changed files with 71 additions and 44 deletions
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@ -53,44 +53,41 @@ uint32_t sys_time_seconds = 0;
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* longest cycle. Here too the above caveats apply.
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*
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* This value is in TIM1/TIM3 timer counts. */
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#define ADC_PRETRIGGER 150 /* trigger with about 12us margin to TIM1 CC IRQ */
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/* Bit timing base value. This is the lowes bit interval used */
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#define PERIOD_BASE 4
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#define ADC_PRETRIGGER 300 /* trigger with about 12us margin to TIM1 CC IRQ */
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/* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set
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* empirically using a debugger and a logic analyzer. */
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#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 120
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#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 240
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/* This is the same as above, but for the reset cycle of the bit period. */
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#define RESET_PERIOD_LENGTH 40
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#define RESET_PERIOD_LENGTH 80
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/* Defines for brevity */
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#define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS
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#define B PERIOD_BASE
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#define B 40
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/* This is a constant offset containing some empirically determined correction values */
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#define C (1 /* reset pulse comp */ - 3 /* analog snafu comp */)
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#define C 0
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/* This lookup table maps bit positions to timer period values. This is a lookup table to allow for the compensation for
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* non-linear effects of ringing at lower bit durations.
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*/
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static uint16_t timer_period_lookup[NBITS] = {
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/* LSB here */
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A + (B<< 0) - C,
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A + (B<< 1) - C,
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A + (B<< 2) - C,
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A + (B<< 3) - C,
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A + (B<< 4) - C,
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A + (B<< 5) - C,
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A + (B<< 6) - C,
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A + (B<< 7) - C,
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A + (B<< 8) - C,
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A + (B<< 9) - C,
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A + (B<<10) - C,
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A + (B<<11) - C,
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A + (B<<12) - C,
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A + (B<<13) - C,
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A + 1,
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A + 3,
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A + 10,
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A + 29,
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A + 70,
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A - C + (B<< 2),
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A - C + (B<< 3),
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A - C + (B<< 4),
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A - C + (B<< 5),
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A - C + (B<< 6),
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A - C + (B<< 7),
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A - C + (B<< 8),
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A - C + (B<< 9),
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A - C + (B<<10),
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/* MSB here */
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};
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@ -182,7 +179,7 @@ int main(void) {
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/* Configure TIM1 for display strobe generation */
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TIM1->CR1 = TIM_CR1_ARPE;
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TIM1->PSC = 1; /* Prescale by 2, resulting in a 15MHz timer frequency and 66.7ns timer step size. */
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TIM1->PSC = 0; /* Prescale by 2, resulting in a 15MHz timer frequency and 66.7ns timer step size. */
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/* CH2 - clear/!MR, CH3 - strobe/STCP */
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TIM1->CCMR2 = (6<<TIM_CCMR2_OC3M_Pos) | TIM_CCMR2_OC3PE | (6<<TIM_CCMR2_OC4M_Pos);
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TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3NE | TIM_CCER_CC3P | TIM_CCER_CC3NP | TIM_CCER_CC4E;
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@ -306,7 +303,7 @@ void TIM1_BRK_UP_TRG_COM_IRQHandler(void) {
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/* Set up the following reset pulse cycle. This cycle is short as it only needs to be long enough for the below
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* part of this ISR handler routine to run. */
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TIM1->ARR = RESET_PERIOD_LENGTH;
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TIM1->CCR3 = 1; /* This value is fixed to produce a very short reset pulse. IOs, PCB and shift registers all can
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TIM1->CCR3 = 2; /* This value is fixed to produce a very short reset pulse. IOs, PCB and shift registers all can
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easily handle this. */
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} else {
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/* Set up everything for the data cycle of the *next* period. The timer is set to count from 0 to ARR. ARR and
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@ -92,13 +92,13 @@ if __name__ == '__main__':
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uut.send_framebuf([0]*uut.nchannels)
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time.sleep(args.wait)
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readings = [ bp.adc_value for _ in range(args.oversample) ]
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mean, stdev = statistics.mean(readings), statistics.stdev(readings)
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zero_mean, stdev = statistics.mean(readings), statistics.stdev(readings)
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cur.execute('''
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INSERT INTO measurements (
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run_id, channel, duty_cycle, voltage, voltage_stdev, timestamp
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) VALUES (?, -1, 0, ?, ?, ?)''',
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(run_id, mean, stdev, time.time()))
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print('Zero cal: {:5.4f}V stdev={:5.4f}V'.format(mean, stdev))
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(run_id, zero_mean, stdev, time.time()))
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print('Zero cal: {:5.4f}V stdev={:5.4f}V'.format(zero_mean, stdev))
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for ch in channels:
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for i in range(nbits):
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@ -123,7 +123,7 @@ if __name__ == '__main__':
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) VALUES (?, ?, ?, ?, ?, ?)''',
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(run_id, ch, duty_cycle, mean, stdev, time.time()))
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print('{:08d} ch={} {:04x}({:6.5f}): {:5.4f} stdev {:5.4f}'.format(
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cur.lastrowid, ch, val, duty_cycle, mean, stdev))
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cur.lastrowid, ch, val, duty_cycle, mean-zero_mean, stdev))
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uut.send_framebuf([0]*uut.nchannels)
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bp.power_on = False
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