79 lines
1.4 KiB
INI
79 lines
1.4 KiB
INI
update=Wed 01 May 2019 02:18:33 PM CEST
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.157
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.157
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TrackWidth2=0.157
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TrackWidth3=0.2
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TrackWidth4=0.4
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TrackWidth5=0.6
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TrackWidth6=0.8
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ViaDiameter1=0.6
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ViaDrill1=0.3
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ViaDiameter2=0.6
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ViaDrill2=0.3
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.09999999999999999
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SilkTextSizeV=0.7
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SilkTextSizeH=0.7
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SilkTextSizeThickness=0.09999999999999999
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.09999999999999999
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.05
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0.051
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SolderMaskMinWidth=0.25
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/1]
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Name=signal
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Clearance=0.157
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TrackWidth=0.157
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ViaDiameter=0.6
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ViaDrill=0.3
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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