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Add end-to-end simulation

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jaseg 2020-03-15 14:47:25 +01:00
parent 0e8a0d6f78
commit fed186a49f
12 changed files with 286 additions and 53 deletions
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12
controller/fw/src/adc.c
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@ -51,8 +51,9 @@ void adc_init() {
ADC1->CR1 = (0<<ADC_CR1_RES_Pos) | (0<<ADC_CR1_DISCNUM_Pos) | ADC_CR1_DISCEN | (0<<ADC_CR1_AWDCH_Pos);
ADC1->CR2 = (1<<ADC_CR2_EXTEN_Pos) | (0<<ADC_CR2_EXTSEL_Pos) | ADC_CR2_DMA | ADC_CR2_ADON | ADC_CR2_DDS;
ADC1->SQR3 = (adc_channel<<ADC_SQR3_SQ3_Pos);
ADC1->SQR3 = (adc_channel<<ADC_SQR3_SQ1_Pos);
ADC1->SQR1 = (0<<ADC_SQR1_L_Pos);
ADC1->SMPR2 = (7<<ADC_SMPR2_SMP0_Pos);
TIM1->CR2 = (2<<TIM_CR2_MMS_Pos); /* Enable update event on TRGO to provide a 1ms reference to rest of system */
TIM1->CCMR1 = (6<<TIM_CCMR1_OC1M_Pos) | (0<<TIM_CCMR1_CC1S_Pos);
@ -86,11 +87,17 @@ void DMA2_Stream0_IRQHandler(void) {
uint8_t isr = (DMA2->LISR >> DMA_LISR_FEIF0_Pos) & 0x3f;
GPIOA->ODR ^= 1<<7;
GPIOA->BSRR = 1<<10;
if (isr & DMA_LISR_TCIF0) { /* Transfer complete */
/* Check we're done processing the old buffer */
if (adc_fft_buf_ready_idx != -1)
if (adc_fft_buf_ready_idx != -1) { /* FIXME DEBUG */
GPIOA->BSRR = 1<<10<<16;
/* clear all flags */
adc_dma->LIFCR = isr<<DMA_LISR_FEIF0_Pos;
return;
panic();
}
/* Kickoff FFT */
int ct = !!(adc_stream->CR & DMA_SxCR_CT);
@ -103,6 +110,7 @@ void DMA2_Stream0_IRQHandler(void) {
if (isr & DMA_LISR_TEIF0) /* Transfer error */
panic();
GPIOA->BSRR = 1<<10<<16;
/* clear all flags */
adc_dma->LIFCR = isr<<DMA_LISR_FEIF0_Pos;
}