Fixup clock config
This commit is contained in:
jaseg
parent
1b7ae0aeef
commit
0e8a0d6f78
3 changed files with 88 additions and 37 deletions
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@ -29,7 +29,7 @@
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/* set parameters required by levmarq() to default values */
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void levmarq_init(LMstat *lmstat)
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{
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lmstat->max_it = 10000;
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lmstat->max_it = 500;
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lmstat->init_lambda = 0.0001f;
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lmstat->up_factor = 10.0f;
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lmstat->down_factor = 10.0f;
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@ -1,4 +1,6 @@
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#include <string.h>
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#include <stm32f407xx.h>
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#include <stm32f4_isr.h>
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@ -9,7 +11,6 @@ uint16_t adc_fft_buf[2][FMEAS_FFT_LEN];
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volatile int adc_fft_buf_ready_idx = -1;
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static DMA_TypeDef *const adc_dma = DMA2;
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static DMA_Stream_TypeDef *const mem_stream = DMA2_Stream1;
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static DMA_Stream_TypeDef *const adc_stream = DMA2_Stream0;
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static const int dma_adc_channel = 0;
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static const int adc_channel = 10;
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@ -37,7 +38,7 @@ void adc_init() {
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while (adc_stream->CR & DMA_SxCR_EN)
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; /* wait for stream to become available */
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adc_stream->NDTR = FMEAS_FFT_LEN/2;
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adc_stream->PAR = &(ADC1->DR);
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adc_stream->PAR = (uint32_t) &(ADC1->DR);
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adc_stream->M0AR = (uint32_t) (adc_fft_buf[0] + FMEAS_FFT_LEN/2);
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adc_stream->M1AR = (uint32_t) (adc_fft_buf[1] + FMEAS_FFT_LEN/2);
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adc_stream->CR = (dma_adc_channel<<DMA_SxCR_CHSEL_Pos) | DMA_SxCR_DBM | (1<<DMA_SxCR_MSIZE_Pos)
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@ -60,35 +61,39 @@ void adc_init() {
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TIM1->ARR = 1000-1; /* 1ms period */
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TIM1->CCR1 = 500-1;
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TIM1->BDTR = TIM_BDTR_MOE;
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/* DEBUG */
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TIM1->DIER = TIM_DIER_CC1IE;
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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NVIC_SetPriority(TIM1_CC_IRQn, 130);
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/* END DEBUG */
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TIM1->CR1 = TIM_CR1_CEN;
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TIM1->EGR = TIM_EGR_UG;
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}
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void TIM1_CC_IRQHandler(void) {
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TIM1->SR &= ~TIM_SR_CC1IF;
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static int foo=0;
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foo++;
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if (foo == 500) {
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foo = 0;
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GPIOA->ODR ^= 1<<6;
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}
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}
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void DMA2_Stream0_IRQHandler(void) {
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uint8_t isr = (DMA2->LISR >> DMA_LISR_FEIF0_Pos) & 0x3f;
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GPIOA->ODR ^= 1<<7;
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if (isr & DMA_LISR_TCIF0) { /* Transfer complete */
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/* Check we're done processing the old buffer */
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if (adc_fft_buf_ready_idx != -1)
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panic();
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/* Kickoff memory DMA into new buffer */
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if (mem_stream->CR & DMA_SxCR_EN)
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panic(); /* We should be long done by now. */
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adc_dma->LIFCR = 0x3d<<DMA_LISR_FEIF1_Pos;
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mem_stream->NDTR = FMEAS_FFT_LEN/2;
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int ct = !!(adc_stream->CR & DMA_SxCR_CT);
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/* back half of old buffer (that was just written) */
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mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct] + FMEAS_FFT_LEN/2);
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/* front half of current buffer (whose back half is being written now) */
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mem_stream->M0AR = (uint32_t) (adc_fft_buf[ct] + 0);
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mem_stream->CR = (1<<DMA_SxCR_MSIZE_Pos) | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_PINC
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| (0<<DMA_SxCR_PL_Pos) | (2<<DMA_SxCR_DIR_Pos);
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mem_stream->CR |= DMA_SxCR_EN;
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/* Kickoff FFT */
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int ct = !!(adc_stream->CR & DMA_SxCR_CT);
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adc_fft_buf_ready_idx = !ct;
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}
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@ -2,6 +2,7 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include <assert.h>
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#include <string.h>
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#include <stm32f407xx.h>
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@ -28,13 +29,19 @@ static void clock_setup(void)
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#define PLL_M 8
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/* Multiply by 336 -> 336 MHz VCO frequency */
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#define PLL_N 336
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/* Divide by 2 -> 168 MHz (max freq for our chip) */
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#define PLL_P 2
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/* Divide by 4 -> 84 MHz (max freq for our chip) */
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#define PLL_P 4
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/* Aux clock for USB OTG, SDIO, RNG: divide VCO frequency (336 MHz) by 7 -> 48 MHz (required by USB OTG) */
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#define PLL_Q 7
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if (((RCC->CFGR & RCC_CFGR_SWS_Msk) >> RCC_CFGR_SW_Pos) != 0)
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asm volatile ("bkpt");
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if (RCC->CR & RCC_CR_HSEON)
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asm volatile ("bkpt");
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RCC->CR |= RCC_CR_HSEON;
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while(!(RCC->CR & RCC_CR_HSERDY));
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while(!(RCC->CR & RCC_CR_HSERDY))
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;
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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@ -46,19 +53,26 @@ static void clock_setup(void)
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/* set AHB prescaler to /1 (CFGR:bits 7:4) */
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RCC->CFGR |= (0 << RCC_CFGR_HPRE_Pos);
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/* set ABP1 prescaler to 4 */
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RCC->CFGR |= (5 << RCC_CFGR_PPRE1_Pos);
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/* set ABP2 prescaler to 2 */
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RCC->CFGR |= (0x4 << RCC_CFGR_PPRE2_Pos);
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/* set ABP1 prescaler to 2 -> 42MHz */
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RCC->CFGR |= (4 << RCC_CFGR_PPRE1_Pos);
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/* set ABP2 prescaler to 1 -> 84MHz */
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RCC->CFGR |= (0 << RCC_CFGR_PPRE2_Pos);
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if (RCC->CR & RCC_CR_PLLON)
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asm volatile ("bkpt");
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/* Configure PLL */
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static_assert(PLL_P % 2 == 0);
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static_assert(PLL_P >= 2 && PLL_P <= 8);
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static_assert(PLL_N >= 50 && PLL_N <= 432);
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static_assert(PLL_M >= 2 && PLL_M <= 63);
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static_assert(PLL_Q >= 2 && PLL_Q <= 15);
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RCC->PLLCFGR = (PLL_M<<RCC_PLLCFGR_PLLM_Pos)
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| (PLL_N << RCC_PLLCFGR_PLLM_Pos)
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uint32_t old = RCC->PLLCFGR & ~(RCC_PLLCFGR_PLLM_Msk
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| RCC_PLLCFGR_PLLN_Msk
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| RCC_PLLCFGR_PLLP_Msk
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| RCC_PLLCFGR_PLLQ_Msk
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| RCC_PLLCFGR_PLLSRC);
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RCC->PLLCFGR = old | (PLL_M<<RCC_PLLCFGR_PLLM_Pos)
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| (PLL_N << RCC_PLLCFGR_PLLN_Pos)
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| ((PLL_P/2 - 1) << RCC_PLLCFGR_PLLP_Pos)
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| (PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
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| RCC_PLLCFGR_PLLSRC; /* select HSE as PLL source */
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@ -71,7 +85,7 @@ static void clock_setup(void)
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/* Configure Flash: enable prefetch, insn cache, data cache; set latency = 5 wait states
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* See reference manual (RM0090), Section 3.5.1, Table 10 (p. 80)
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*/
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | (5<<FLASH_ACR_LATENCY);
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | (5<<FLASH_ACR_LATENCY_Pos);
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/* Select PLL as system clock source */
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RCC->CFGR &= ~RCC_CFGR_SW_Msk;
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@ -84,6 +98,7 @@ static void clock_setup(void)
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static void led_setup(void)
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{
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
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GPIOA->MODER |= (1<<GPIO_MODER_MODER6_Pos) | (1<<GPIO_MODER_MODER7_Pos);
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}
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@ -148,25 +163,56 @@ static uint32_t debug_last_freq = 0;
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int main(void)
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{
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/* DEBUG */
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/* MCO2 */
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
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GPIOC->MODER &= ~GPIO_MODER_MODER9_Msk;
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GPIOC->MODER |= (2<<GPIO_MODER_MODER9_Pos);
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GPIOC->AFR[1] &= ~GPIO_AFRH_AFSEL9_Msk;
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GPIOC->OSPEEDR |= (3<<GPIO_OSPEEDR_OSPEED9_Pos); /* SCK */
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RCC->CFGR |= (6<<RCC_CFGR_MCO2PRE_Pos) | (3<<RCC_CFGR_MCO2_Pos);
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/* END DEBUG */
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clock_setup();
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led_setup();
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/*
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spi_flash_setup();
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adc_init();
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*/
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/* DEBUG */
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/* TIM1 CC1 */
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GPIOA->MODER &= ~GPIO_MODER_MODER8_Msk;
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GPIOA->MODER |= (2<<GPIO_MODER_MODER8_Pos);
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GPIOA->AFR[1] &= ~GPIO_AFRH_AFSEL8_Msk;
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GPIOA->AFR[1] |= 1<<GPIO_AFRH_AFSEL8_Pos;
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/* END DEBUG */
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int cnt = 0;
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while (23) {
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if (cnt++ == 100000) {
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cnt = 0;
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GPIOA->ODR ^= 1<<6;
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}
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if (adc_fft_buf_ready_idx != -1) {
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/*
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memcpy(adc_fft_buf[!adc_fft_buf_ready_idx], adc_fft_buf[adc_fft_buf_ready_idx] + FMEAS_FFT_LEN/2, sizeof(adc_fft_buf[0][0]) * FMEAS_FFT_LEN/2);
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#if 0
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float out;
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if (adc_buf_measure_freq(adc_fft_buf[adc_fft_buf_ready_idx], &out)) {
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measurement_errors++;
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continue;
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debug_last_freq = -1;
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} else {
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debug_last_freq = out;
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/*
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dsss_demod_init(&demod_state);
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dsss_demod_step(&demod_state, out, freq_sample_ts);
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*/
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}
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debug_last_freq = out;
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dsss_demod_init(&demod_state);
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dsss_demod_step(&demod_state, out, freq_sample_ts);
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*/
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#endif
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freq_sample_ts++; /* TODO: also increase in case of freq measurement error? */
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adc_fft_buf_ready_idx = -1;
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