94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
#ifndef __ADC_INTERFACE_H__
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#define __ADC_INTERFACE_H__
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enum adc_reg_addr {
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ADC_REG_ID = 0x00,
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ADC_REG_STATUS = 0x01,
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ADC_REG_MODE = 0x02,
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ADC_REG_CLOCK = 0x03,
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ADC_REG_GAIN = 0x04,
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ADC_REG_CFG = 0x06,
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ADC_REG_THRSHLD_MSB = 0x07,
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ADC_REG_THRSHLD_LSB = 0x08,
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ADC_REG_CH0_CFG = 0x09,
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ADC_REG_CH0_OCAL_MSB = 0x0a,
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ADC_REG_CH0_OCAL_LSB = 0x0b,
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ADC_REG_CH0_GCAL_MSB = 0x0c,
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ADC_REG_CH0_GCAL_LSB = 0x0d,
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ADC_REG_CH1_CFG = 0x0e,
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ADC_REG_CH1_OCAL_MSB = 0x0f,
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ADC_REG_CH1_OCAL_LSB = 0x10,
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ADC_REG_CH1_GCAL_MSB = 0x11,
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ADC_REG_CH1_GCAL_LSB = 0x12,
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ADC_REG_REGMAP_CRC = 0x3e,
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};
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#define ADC_STATUS_LOCK (1<<15)
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#define ADC_STATUS_F_RESYNC (1<<14)
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#define ADC_STATUS_REG_MAP (1<<13)
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#define ADC_STATUS_CRC_ERR (1<<12)
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#define ADC_STATUS_CRC_TYPE (1<<11)
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#define ADC_STATUS_RESET (1<<10)
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#define ADC_STATUS_WLENGTH_Pos 8
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#define ADC_STATUS_DRDY1 (1<<1)
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#define ADC_STATUS_DRDY0 (1<<0)
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#define ADC_MODE_REG_CRC_EN (1<<13)
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#define ADC_MODE_RX_CRC_EN (1<<12)
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#define ADC_MODE_CRC_TYPE (1<<11)
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#define ADC_MODE_RESET (1<<10)
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#define ADC_MODE_WLENGTH_Pos 8
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#define ADC_MODE_TIMEOUT (1<<4)
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#define ADC_MODE_DRDY_SEL_Pos 2
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#define ADC_MODE_DRDY_HiZ (1<<1)
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#define ADC_MODE_DRDY_FMT (1<<0)
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#define ADC_CLOCK_CH1_EN (1<<9)
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#define ADC_CLOCK_CH2_EN (1<<8)
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#define ADC_CLOCK_TBM (1<<5)
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#define ADC_CLOCK_OSR_Pos 2
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#define ADC_CLOCK_PWR_Pos 0
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#define ADC_CLOCK_OSR_64 ADC_CLOCK_TBM
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#define ADC_CLOCK_OSR_128 (0<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_256 (1<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_512 (2<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_1024 (3<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_2048 (4<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_4096 (5<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_8192 (6<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_OSR_16384 (7<<ADC_CLOCK_OSR_Pos)
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#define ADC_CLOCK_PWR_VERY_LOW (0<<ADC_CLOCK_PWR_Pos)
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#define ADC_CLOCK_PWR_LOW (1<<ADC_CLOCK_PWR_Pos)
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#define ADC_CLOCK_PWR_HIRES (2<<ADC_CLOCK_PWR_Pos)
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#define ADC_GAIN1_PGAGAIN1_1 (0<<4)
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#define ADC_GAIN1_PGAGAIN1_2 (1<<4)
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#define ADC_GAIN1_PGAGAIN1_4 (2<<4)
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#define ADC_GAIN1_PGAGAIN1_8 (3<<4)
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#define ADC_GAIN1_PGAGAIN1_16 (4<<4)
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#define ADC_GAIN1_PGAGAIN1_32 (5<<4)
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#define ADC_GAIN1_PGAGAIN1_64 (5<<4)
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#define ADC_GAIN1_PGAGAIN1_128 (7<<4)
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#define ADC_GAIN1_PGAGAIN0_1 (0<<0)
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#define ADC_GAIN1_PGAGAIN0_2 (1<<0)
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#define ADC_GAIN1_PGAGAIN0_4 (2<<0)
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#define ADC_GAIN1_PGAGAIN0_8 (3<<0)
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#define ADC_GAIN1_PGAGAIN0_16 (4<<0)
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#define ADC_GAIN1_PGAGAIN0_32 (5<<0)
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#define ADC_GAIN1_PGAGAIN0_64 (5<<0)
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#define ADC_GAIN1_PGAGAIN0_128 (7<<0)
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#define ADC_CFG_GC_DLY_Pos 9
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#define ADC_CFG_GC_EN (1<<8)
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#define ADC_CFG_CD_ALLCH (1<<7)
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#define ADC_CFG_CD_NUM_Pos 4
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#define ADC_CFG_CD_LEN_Pos 1
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#define ADC_CFG_CD_EN (1<<0)
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#define ADC_CHn_CFG_PHASE_Pos 6
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#define ADC_CHn_CFG_DCBLK_DIS (1<<2)
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#define ADC_CHn_CFG_MUX_Pos 0
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#endif /* __ADC_INTERFACE_H__ */
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