WIP

src/main.c

@@ -1,5 +1,6 @@
 
 #include <global.h>
+#include <irqs.h>
 #include <stdarg.h>
 
 struct adc_state {
@@ -175,17 +176,18 @@ void adc_sm(bool reset) {
 }
 
 void adc_init() {
-    SPI1->CR1 = (1<<SPI_CR1_BR_Pos) | SPI_CR1_MSTR | SPI_CR1_CPHA;
-    SPI1->CR2 = (0x7<<SPI_CR2_DS_Pos) | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; /* 8 bit frames, all DMA all the time */
+    memset(&st_adc, 0, sizeof(st_adc));
+    SPI1->CR1 = (1<<SPI_CR1_BR_Pos) | SPI_CR1_MSTR | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_CPHA;
+    SPI1->CR2 = (0x7<<SPI_CR2_DS_Pos) | SPI_CR2_FRXTH | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; /* 8 bit frames, all DMA all the time */
     SPI1->CR1 |= SPI_CR1_SPE;
-    
+
     /* CH1 -> DRDY/TIM2-triggered start of conversion */
     DMA1_Channel1->CCR = (1<<DMA_CCR_MSIZE_Pos) | (1<<DMA_CCR_PSIZE_Pos) | DMA_CCR_TEIE | DMA_CCR_DIR | DMA_CCR_CIRC;
     DMA1_Channel1->CMAR = (uint32_t)&st_adc.dma_ccr3;
     DMA1_Channel1->CPAR = (uint32_t)&(DMA1_Channel3->CCR);
     DMA1_Channel1->CNDTR = 1;
     /* CH2 -> RX DMA: 8 bit peripheral -> 8 bit memory */
-    DMA1_Channel2->CCR = (0<<DMA_CCR_MSIZE_Pos) | (0<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_TEIE | DMA_CCR_CIRC;
+    DMA1_Channel2->CCR = (0<<DMA_CCR_MSIZE_Pos) | (0<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_TEIE | DMA_CCR_TCIE | DMA_CCR_CIRC;
     DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR);
     DMA1_Channel2->CMAR = (uint32_t)&st_adc.rxbuf;
     /* CH3 -> TX DMA: 8 bit memory -> 8 bit peripheral */
@@ -204,6 +206,10 @@ void adc_init() {
 
     st_adc.dma_ccr3 = DMA1_Channel3->CCR | DMA_CCR_EN;
     st_adc.response_bytes = 3;
+
+    NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+    NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+
     adc_sm(true);
 }
 
@@ -212,7 +218,6 @@ void DMA1_Channel1_IRQHandler() {
     if (flags & (DMA_ISR_TEIF1)) {
         DMA1->IFCR = DMA_IFCR_CTEIF1;
         asm volatile ("bkpt");
-
     }
 }
 
@@ -297,16 +302,16 @@ void adc_setup_dma(size_t tx_bytes, size_t response_bytes) {
 
 int main(void) {
     /* Enable HSE w/ 8 MHz crystal */
-    RCC->CR |= RCC_CR_HSEON;
-    while (!(RCC->CR & RCC_CR_HSERDY))
-        ;
-    asm volatile ("bkpt");
+    /* FIXME */
+    //RCC->CR |= RCC_CR_HSEON;
+    //while (!(RCC->CR & RCC_CR_HSERDY))
+    //    ;
 
     /* Configure PLL multiplier, clock dividers and MCO */
     /* The ADS131M02 datasheet recommends an 8.192 MHz input clock for high-resolution mode. */
-    RCC->CFGR = (6<<RCC_CFGR_MCO_Pos)    | /* Forward 8 MHz HSE to MCO 1:1 */
+    RCC->CFGR = (5<<RCC_CFGR_MCO_Pos)    | /* Forward 8 MHz HSI to MCO 1:1 */
                 (4<<RCC_CFGR_PLLMUL_Pos) | /* Set PLL multiplier to 6x, leave divider at 1 */
-                (2<<RCC_CFGR_PLLSRC_Pos) | /* Select HSE as PLL source */
+                (1<<RCC_CFGR_PLLSRC_Pos) | /* Select HSI as PLL source */
                 /* Leave HPRE at 1, not dividing clock. */
                 (4<<RCC_CFGR_PPRE_Pos);    /* Use SYSCLK / 2 for APB bus clock */
 
@@ -314,13 +319,13 @@ int main(void) {
     RCC->CR |= RCC_CR_PLLON;
     while (!(RCC->CR & RCC_CR_PLLRDY))
         ;
-    asm volatile ("bkpt");
+
+    FLASH->ACR = FLASH_ACR_PRFTBE | (1<<FLASH_ACR_LATENCY_Pos);
 
     /* Switch system clock to PLL */
     RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
     while (((RCC->CFGR & RCC_CFGR_SWS_Msk) >> RCC_CFGR_SWS_Pos) != 2)
         ;
-    asm volatile ("bkpt");
 
     /* Enable peripheral clocks */
     RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_DMAEN;
@@ -328,9 +333,6 @@ int main(void) {
     RCC->APB1ENR |= RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN | RCC_APB1ENR_SPI2EN | RCC_APB1ENR_USART3EN |
         RCC_APB1ENR_I2C1EN | RCC_APB1ENR_USBEN;
 
-    asm volatile ("bkpt");
-    adc_init();
-
 #define AFRL(pin, val) ((val) << ((pin)*4))
 #define AFRH(pin, val) ((val) << (((pin)-8)*4))
 #define AF(pin) (2<<(2*(pin)))
@@ -368,6 +370,16 @@ int main(void) {
                     AFRH( 9, 1) | /* USART1 TX (debug USART) */
                     AFRH(10, 1);  /* USART1 RX */
     GPIOA->BSRR = 1<<2; /* De-assert ADC !CS */
+    GPIOA->OSPEEDR = (3<<GPIO_OSPEEDR_OSPEEDR1_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR2_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR5_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR6_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR7_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR8_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR9_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR10_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR13_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR14_Pos);
     
     /* GPIOB: 
      *  0 -  BT2
@@ -400,6 +412,13 @@ int main(void) {
                     AFRH(13, 0) | /* SPI2 SCK (LEDs) */
                     AFRH(14, 4) | /* USART3 RTS (RS485 DE via remap in USART regs) */
                     AFRH(15, 0);  /* SPI2 HOPI */
+    GPIOB->OSPEEDR = (3<<GPIO_OSPEEDR_OSPEEDR6_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR7_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR10_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR11_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR13_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR14_Pos) |
+                     (3<<GPIO_OSPEEDR_OSPEEDR15_Pos);
 
     /* GPIOC:
      * PC13 - DFU button
@@ -427,6 +446,10 @@ int main(void) {
     }
 }
 
+void HardFault_Handler() {
+    asm volatile ("bkpt");
+}
+
 void *memcpy(void *restrict dest, const void *restrict src, size_t n)
 {
 	unsigned char *d = dest;