jaseg
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cf874f6723
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add firmware skeleton
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2025-11-28 22:11:33 +01:00 |
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jaseg
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4b36aa8b6b
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Add link tia test board
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2025-02-21 19:44:01 +01:00 |
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jaseg
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8e93d7f7a9
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WIP
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2025-01-20 22:23:57 +01:00 |
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jaseg
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7afac30aab
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Initial layout WIP
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2025-01-18 15:00:56 +01:00 |
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jaseg
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00c46c293a
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WIP
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2025-01-17 23:51:54 +01:00 |
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jaseg
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0fda5c8614
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First mainboard layout draft done
Still missing: mesh hookup, layer interconnect, optical link
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2025-01-17 23:51:07 +01:00 |
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jaseg
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695b58ef9f
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Layout WIP
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2025-01-16 18:42:35 +01:00 |
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jaseg
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37674158d4
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Finish power section
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2025-01-15 22:18:55 +01:00 |
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jaseg
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6538b159d1
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WIP
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2025-01-15 21:40:14 +01:00 |
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jaseg
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0a4aed147b
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Initial commit
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2025-01-13 20:39:54 +01:00 |
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