Layout: done!

card_base/card_base-cache.lib

@@ -162,26 +162,6 @@ X - 2 0 -100 100 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_CP_Small
-#
-DEF Device_CP_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_CP_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- CP_*
-$ENDFPLIST
-DRAW
-S -60 -12 60 -27 0 1 0 F
-S -60 27 60 12 0 1 0 N
-P 2 0 1 0 -50 60 -30 60 N
-P 2 0 1 0 -40 50 -40 70 N
-X ~ 1 0 100 73 D 50 50 1 1 P
-X ~ 2 0 -100 73 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
 # Device_C_Small
 #
 DEF Device_C_Small C 0 10 N N 1 F N

card_base/card_base.pro

@@ -1,30 +1,10 @@
-update=05/04/2019 20:44:53
+update=Mon May  6 12:07:10 2019
 version=1
 last_client=kicad
 [general]
 version=1
 RootSch=
 BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-CopperEdgeClearance=0.000000000000
 [cvpcb]
 version=1
 NetIExt=net
@@ -32,3 +12,248 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=card_base.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.09999999999999999
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+CopperEdgeClearance=0
+TrackWidth1=0.1
+TrackWidth2=0.1
+TrackWidth3=0.15
+TrackWidth4=0.2
+TrackWidth5=0.3
+TrackWidth6=0.45
+TrackWidth7=0.6
+TrackWidth8=0.9
+TrackWidth9=1.25
+TrackWidth10=1.6
+TrackWidth11=2.2
+ViaDiameter1=0.8
+ViaDrill1=0.4
+ViaDiameter2=0.8
+ViaDrill2=0.4
+ViaDiameter3=1.2
+ViaDrill3=0.6
+ViaDiameter4=1.6
+ViaDrill4=0.8
+ViaDiameter5=2
+ViaDrill5=1.2
+ViaDiameter6=2.6
+ViaDrill6=1.8
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.051
+SolderMaskMinWidth=0.25
+SolderPasteClearance=0
+SolderPasteRatio=0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.1
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25

card_base/footprints.pretty/apds9960.kicad_mod

@@ -0,0 +1,37 @@
+(module "apds9960" (layer F.Cu) (tedit 5CCE6FAE)
+  (fp_text reference "REF**" (at 0 -4.365) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value "apds9960" (at 0 -5.82) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -1.2 -2) (end 1.2 -2) (layer F.SilkS) (width 0.2))
+  (fp_line (start 1.2 -2) (end 1.2 2) (layer F.SilkS) (width 0.2))
+  (fp_line (start 1.2 2) (end -1.2 2) (layer F.SilkS) (width 0.2))
+  (fp_line (start -1.2 2) (end -1.2 -2) (layer F.SilkS) (width 0.2))
+  (fp_circle (center 1.2 -2) (end 1.75 -2) (layer F.SilkS) (width 0.2))
+  (pad "1" smd rect (at 0.7 -1.455 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "2" smd rect (at 0.7 -0.485 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "3" smd rect (at 0.7 0.485 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "4" smd rect (at 0.7 1.455 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "5" smd rect (at -0.7 1.455 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "6" smd rect (at -0.7 0.485 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "7" smd rect (at -0.7 -0.485 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "8" smd rect (at -0.7 -1.455 180) (size 0.6 0.72) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "1" smd rect (at 2.25 -1.455 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "2" smd rect (at 2.25 -0.485 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "3" smd rect (at 2.25 0.485 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "4" smd rect (at 2.25 1.455 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "8" smd rect (at -2.25 -1.455 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "7" smd rect (at -2.25 -0.485 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "6" smd rect (at -2.25 0.485 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "5" smd rect (at -2.25 1.455 180) (size 1.5 0.72) (layers "F.Cu" "F.Mask"))
+  (pad "1" smd rect (at 1.5 -1.455 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "2" smd rect (at 1.5 -0.485 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "3" smd rect (at 1.5 0.485 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "4" smd rect (at 1.5 1.455 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "5" smd rect (at -1.5 1.455 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "6" smd rect (at -1.5 0.485 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "7" smd rect (at -1.5 -0.485 180) (size 1.5 0.72) (layers "F.Cu"))
+  (pad "8" smd rect (at -1.5 -1.455 180) (size 1.5 0.72) (layers "F.Cu"))
+)

card_base/footprints.pretty/cr2032_holder_through_board.kicad_mod

@@ -0,0 +1,76 @@
+(module "cr2032_holder_through_board" (layer F.Cu) (tedit 5CCE6B90)
+  (descr "http://www.keyelco.com/product-pdf.cfm?p=726")
+  (tags "CR2032 BR2032 BatteryHolder Battery")
+  (attr smd)
+  (fp_text reference "REF**" (at -14.125 -5.3) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value "cr2032_holder_through_board" (at 0 -11.75) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_circle (center 0 0) (end -10.2 0) (layer Dwgs.User) (width 0.3))
+  (fp_line (start 11 8) (end -9.4 8) (layer F.Fab) (width 0.1))
+  (fp_line (start 11 -8) (end -11 -8) (layer F.Fab) (width 0.1))
+  (fp_line (start 11 8) (end 11 3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start 11 -8) (end 11 -3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -11 -8) (end -11 -3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -11 6.4) (end -11 3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -11 3.5) (end -14.2 3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -14.2 3.5) (end -14.2 -3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -14.2 -3.5) (end -11 -3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start 11 3.5) (end 14.2 3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start 14.2 3.5) (end 14.2 -3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start 14.2 -3.5) (end 11 -3.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -9.4 8) (end -11 6.4) (layer F.Fab) (width 0.1))
+  (fp_line (start 11.35 3.85) (end 14.55 3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start 14.55 3.85) (end 14.55 2.3) (layer F.SilkS) (width 0.12))
+  (fp_line (start 11.35 8.35) (end 11.35 3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start 11.35 8.35) (end -9.55 8.35) (layer F.SilkS) (width 0.12))
+  (fp_line (start -11.35 6.55) (end -11.35 3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start -9.55 8.35) (end -11.35 6.55) (layer F.SilkS) (width 0.12))
+  (fp_line (start -11.35 3.85) (end -14.55 3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start -14.55 3.85) (end -14.55 2.3) (layer F.SilkS) (width 0.12))
+  (fp_line (start -11.35 -3.85) (end -14.55 -3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start -14.55 -3.85) (end -14.55 -2.3) (layer F.SilkS) (width 0.12))
+  (fp_line (start 11.35 -3.85) (end 14.55 -3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start 14.55 -3.85) (end 14.55 -2.3) (layer F.SilkS) (width 0.12))
+  (fp_line (start -11.35 -8.35) (end 11.35 -8.35) (layer F.SilkS) (width 0.12))
+  (fp_line (start -11.35 -8.35) (end -11.35 -3.85) (layer F.SilkS) (width 0.12))
+  (fp_line (start 11.35 -8.35) (end 11.35 -3.85) (layer F.SilkS) (width 0.12))
+  (fp_arc (start 0 0) (end -6.5 8.5) (angle -74.81070976) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 11.5 8.5) (end 6.5 8.5) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -6.5 8.5) (end -11.5 8.5) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -11.5 4) (end -11.5 8.5) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -14.7 4) (end -11.5 4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -14.7 4) (end -14.7 2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -14.7 2.3) (end -16.45 2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -16.45 2.3) (end -16.45 -2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -14.7 -2.3) (end -16.45 -2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -14.7 -2.3) (end -14.7 -4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -14.7 -4) (end -11.5 -4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -11.5 -4) (end -11.5 -8.5) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -11.5 -8.5) (end -6.5 -8.5) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 11.5 -8.5) (end 11.5 -4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 11.5 -4) (end 14.7 -4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 14.7 -4) (end 14.7 -2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 14.7 -2.3) (end 16.45 -2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 16.45 -2.3) (end 16.45 2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 16.45 2.3) (end 14.7 2.3) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 14.7 2.3) (end 14.7 4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 14.7 4) (end 11.5 4) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 11.5 4) (end 11.5 8.5) (layer F.CrtYd) (width 0.05))
+  (fp_arc (start 0 0) (end 6.5 -8.5) (angle -74.81070976) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 11.5 -8.5) (end 6.5 -8.5) (layer F.CrtYd) (width 0.05))
+  (fp_text user "%R" (at 0 0) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -13 5) (end -13 7) (layer F.SilkS) (width 0.12))
+  (fp_line (start -12 6) (end -14 6) (layer F.SilkS) (width 0.12))
+  (pad "2" smd rect (at 15.75 0 180) (size 5 4) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (pad "1" smd rect (at -15.75 0 180) (size 5 4) (layers "F.Cu" "F.Paste" "F.Mask"))
+  (model "${KISYS3DMOD}/Battery.3dshapes/BatteryHolder_Keystone_1060_1x2032.wrl"
+    (at (xyz 0 0 0))
+    (scale (xyz 1 1 1))
+    (rotate (xyz 0 0 0))
+  )
+)

card_base/fp-info-cache

@@ -0,0 +1,15 @@
+3114064716112
+footprints
+apds9960
+
+
+0
+24
+8
+footprints
+cr2032_holder_through_board
+http://www.keyelco.com/product-pdf.cfm?p=726
+CR2032{space}BR2032{space}BatteryHolder{space}Battery
+0
+2
+2

card_base/fp-lib-table

@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name "footprints")(type "KiCad")(uri "${KIPRJMOD}/footprints.pretty")(options "")(descr ""))
+)