143 lines
6.2 KiB
C
143 lines
6.2 KiB
C
/**
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******************************************************************************
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* @file system_stm32f4xx.c
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* @author MCD Application Team
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* @version V1.1.0
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* @date 17-February-2017
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be
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*used
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* by the user application to setup the
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*SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and
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*must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without
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*modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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*notice,
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* this list of conditions and the following disclaimer in the
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*documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its
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*contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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*ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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*LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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*USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include "stm32f4xx.h"
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#if !defined(HSE_VALUE)
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#if defined(USE_STM32469I_DISCO_REVA)
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#define HSE_VALUE \
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((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
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#else
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#define HSE_VALUE \
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((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
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#endif /* USE_STM32469I_DISCO_REVA */
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#endif /* HSE_VALUE */
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#if !defined(HSI_VALUE)
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#define HSI_VALUE \
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((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#define VECT_TAB_OFFSET 0x00 /* This value must be a multiple of 0x200. */
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/* The following variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions
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listed above, since the SystemCoreClock variable is updated automatically. */
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uint32_t SystemCoreClock = 16000000;
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const uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0,
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1, 2, 3, 4, 6, 7, 8, 9 };
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const uint8_t APBPrescTable[8] = { 0, 0, 0, 0, 1, 2, 3, 4 };
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/* Setup the microcontroller system: Initialize the FPU setting, vector table location and External memory configuration. */
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void SystemInit(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state */
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RCC->CR |= (uint32_t)0x00000001; /* Set HSION bit */
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RCC->CFGR = 0x00000000; /* Reset CFGR register */
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RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEON, CSSON and PLLON bits */
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RCC->PLLCFGR = 0x24003010; /* Reset PLLCFGR register */
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RCC->CR &= (uint32_t)0xFFFBFFFF; /* Reset HSEBYP bit */
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RCC->CIR = 0x00000000; /* Disable all interrupts */
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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}
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/* Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core
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* clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters. */
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void SystemCoreClockUpdate(void)
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{
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switch (RCC->CFGR & RCC_CFGR_SWS) {
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case 0x00: /* HSI */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: {/* PLL */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P */
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uint32_t pllvco;
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uint32_t pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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uint32_t pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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if (pllsource != 0) /* HSE */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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else /* HSI */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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uint32_t pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
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SystemCoreClock = pllvco / pllp;
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break; }
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK frequency */
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SystemCoreClock >>= AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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}
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