jaseg
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80201a7666
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Make a really fancy diagram
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2018-12-11 23:34:11 +09:00 |
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jaseg
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acc0cf2d9e
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pcb: Fix a bunch of kicady layout errors
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2018-11-29 17:27:14 +09:00 |
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jaseg
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8e1bf42f39
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Some small fixes, add silk artwork
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2018-11-29 10:18:56 +09:00 |
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jaseg
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ad86b13649
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pcb: Add project info to silk and do gerber export
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2018-11-27 11:37:35 +09:00 |
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jaseg
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2de3660f50
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PCB silk: hide testpoint references
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2018-11-22 10:21:26 +09:00 |
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jaseg
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47f48bea90
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Further PCB cleanup, initial silk cleanup
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2018-11-22 10:17:35 +09:00 |
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jaseg
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07ae18740e
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Some cleanups
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2018-11-21 23:05:42 +09:00 |
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jaseg
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bd93c5e229
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Initial PCB draft
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2018-11-21 22:18:37 +09:00 |
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jaseg
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194bd7fdb9
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Initial schematic commit
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2018-11-17 11:35:25 +09:00 |
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