jaseg/secure-hid
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pcb: Add BOM

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jaseg 2018-11-27 17:14:46 +09:00
parent ad86b13649
commit 9e50656e35
11 changed files with 3645 additions and 10 deletions
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pcb/securehid.bak
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@ -1235,7 +1235,7 @@ F 1 "AO3400" H 9556 9745 50 0000 L CNN
F 2 "TO_SOT_Packages_SMD:SOT-23" H 9550 9625 50 0001 L CIN
F 3 "https://www.fairchildsemi.com/datasheets/2N/2N7002.pdf" H 9350 9700 50 0001 L CNN
1 9350 9700
-1 0 0 1
-1 0 0 -1
$EndComp
$Comp
L device:LED D4
@ -1509,7 +1509,7 @@ F 1 "AO3400" H 8256 10595 50 0000 L CNN
F 2 "TO_SOT_Packages_SMD:SOT-23" H 8250 10475 50 0001 L CIN
F 3 "https://www.fairchildsemi.com/datasheets/2N/2N7002.pdf" H 8050 10550 50 0001 L CNN
1 8050 10550
-1 0 0 1
-1 0 0 -1
$EndComp
Wire Wire Line
7950 10350 7950 10300
@ -1593,7 +1593,6 @@ Wire Wire Line
7950 10750 7950 10850
Wire Wire Line
7950 10750 8500 10750
Connection ~ 7950 10750
Wire Wire Line
8900 10550 9400 10550
Text Label 9400 10550 2 50 ~ 0
@ -4070,10 +4069,10 @@ Connection ~ 14400 3650
Wire Wire Line
14400 3650 15100 3650
$Comp
L Connector:TestPoint_Alt TP?
L Connector:TestPoint_Alt TP83
U 1 1 5C13B94B
P 14400 3700
F 0 "TP?" V 14400 4000 50 0000 C CNN
F 0 "TP83" V 14400 4000 50 0000 C CNN
F 1 "TestPoint_Alt" V 14504 3774 50 0001 C CNN
F 2 "TestPoint:TestPoint_Pad_1.0x1.0mm" H 14600 3700 50 0001 C CNN
F 3 "~" H 14600 3700 50 0001 C CNN
@ -4081,14 +4080,17 @@ F 3 "~" H 14600 3700 50 0001 C CNN
0 -1 -1 0
$EndComp
$Comp
L power:GNDA #PWR?
L power:GNDA #PWR0160
U 1 1 5C14109B
P 14400 3700
F 0 "#PWR?" H 14400 3450 50 0001 C CNN
F 0 "#PWR0160" H 14400 3450 50 0001 C CNN
F 1 "GNDA" H 14405 3527 50 0000 C CNN
F 2 "" H 14400 3700 50 0001 C CNN
F 3 "" H 14400 3700 50 0001 C CNN
1 14400 3700
1 0 0 -1
$EndComp
Text Notes 12150 6300 0 50 ~ 0
Todo:\n- Fix 32kHz crystal footprint to something available\n- Fix CR2032 holder footprint to top-loading type\n- Fix MicroUSB footprint (cross-check against stuff that can be bought)
Connection ~ 7950 10750
$EndSCHEMATC