Removed ROM_ function prefixes. The linker should be able to handle this
This commit is contained in:
jaseg
parent
cc9378fe4f
commit
e4fe36e15f
1 changed files with 52 additions and 52 deletions
104
firmware/main.c
104
firmware/main.c
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@ -105,10 +105,10 @@ void SysTickIntHandler(void) {
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/* Will be called when a DMA transfer is complete */
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void SSI0IntHandler(void) {
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/* FIXME is this necessary? */
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unsigned long ssistatus = ROM_SSIIntStatus(SSI0_BASE, 1);
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ROM_SSIIntClear(SSI0_BASE, ssistatus);
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unsigned long ssistatus = SSIIntStatus(SSI0_BASE, 1);
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SSIIntClear(SSI0_BASE, ssistatus);
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if(!ROM_uDMAChannelIsEnabled(11)){
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if(!uDMAChannelIsEnabled(11)){
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/* A TX DMA transfer was completed */
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/* FIXME actually, just set a flag here and kick off when all four controllers signal completion.*/
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/* Wait 1.2ms for the WS2801s to latch (the datasheet specifies at least 500µs) */
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@ -195,38 +195,38 @@ void kickoff_transfers() {
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}
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void kickoff_transfer(unsigned int channel, unsigned int offset, int base) {
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ROM_uDMAChannelTransferSet(channel | UDMA_PRI_SELECT, UDMA_MODE_BASIC, framebuffer_output+BUS_SIZE*offset, (void *)(base + SSI_O_DR), BUS_SIZE);
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ROM_uDMAChannelEnable(channel);
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uDMAChannelTransferSet(channel | UDMA_PRI_SELECT, UDMA_MODE_BASIC, framebuffer_output+BUS_SIZE*offset, (void *)(base + SSI_O_DR), BUS_SIZE);
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uDMAChannelEnable(channel);
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}
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void ssi_udma_channel_config(unsigned int channel) {
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/* Set the USEBURST attribute for the uDMA SSI TX channel. This will force the controller to always use a burst
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* when transferring data from the TX buffer to the SSI. This is somewhat more effecient bus usage than the default
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* which allows single or burst transfers. */
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ROM_uDMAChannelAttributeEnable(channel, UDMA_ATTR_USEBURST);
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uDMAChannelAttributeEnable(channel, UDMA_ATTR_USEBURST);
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/* Configure the SSI Tx µDMA Channel to transfer from RAM to TX FIFO. The arbitration size is set to 4, which
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* matches the SSI TX FIFO µDMA trigger threshold. */
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ROM_uDMAChannelControlSet(channel | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4);
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uDMAChannelControlSet(channel | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4);
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}
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int main(void) {
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/* Enable lazy stacking for interrupt handlers. This allows floating-point instructions to be used within interrupt
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* handlers, but at the expense of extra stack usage. */
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ROM_FPULazyStackingEnable();
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FPULazyStackingEnable();
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/* Set clock to PLL at 50MHz */
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
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SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
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SYSCTL_XTAL_16MHZ);
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/* Configure UART0 pins */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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GPIOPinConfigure(GPIO_PA0_U0RX);
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GPIOPinConfigure(GPIO_PA1_U0TX);
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ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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/* Enable the GPIO pins for the LED (PF2 & PF3). */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3|GPIO_PIN_2);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3|GPIO_PIN_2);
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UARTStdioInit(0);
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UARTprintf("Booting...\n\n");
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@ -234,80 +234,80 @@ int main(void) {
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g_bUSBConfigured = false;
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/* Enable the GPIO peripheral used for USB, and configure the USB pins. */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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ROM_GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5);
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/* Enable the system tick. FIXME do we need this? */
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ROM_SysTickPeriodSet(ROM_SysCtlClockGet() / SYSTICKS_PER_SECOND);
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ROM_SysTickIntEnable();
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ROM_SysTickEnable();
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SysTickPeriodSet(SysCtlClockGet() / SYSTICKS_PER_SECOND);
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SysTickIntEnable();
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SysTickEnable();
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/* Configure USB */
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USBBufferInit((tUSBBuffer *)&g_sRxBuffer);
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USBStackModeSet(0, USB_MODE_FORCE_DEVICE, 0);
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USBDBulkInit(0, (tUSBDBulkDevice *)&g_sBulkDevice);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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GPIOPinConfigure(GPIO_PA2_SSI0CLK);
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GPIOPinConfigure(GPIO_PA5_SSI0TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_5);
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GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_5);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
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GPIOPinConfigure(GPIO_PB4_SSI2CLK);
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GPIOPinConfigure(GPIO_PB7_SSI2TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_7);
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GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_7);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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GPIOPinConfigure(GPIO_PD0_SSI3CLK);
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GPIOPinConfigure(GPIO_PD3_SSI3TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_3);
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GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_3);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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GPIOPinConfigure(GPIO_PF2_SSI1CLK);
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GPIOPinConfigure(GPIO_PF1_SSI1TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_1);
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GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_1);
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/* Configure SSI0..3 for the ws2801's SPI-like protocol */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
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/* 200kBd */
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SSIConfigSetExpClk(SSI0_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI1_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI2_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI3_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI2_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
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/* Configure the µDMA controller for use by the SPI interface */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
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ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
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// FIXME what do we need this for? ROM_IntEnable(INT_UDMAERR); // Enable µDMA error interrupt
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ROM_uDMAEnable();
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ROM_uDMAControlBaseSet(ucControlTable);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
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SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
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// FIXME what do we need this for? IntEnable(INT_UDMAERR); // Enable µDMA error interrupt
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uDMAEnable();
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uDMAControlBaseSet(ucControlTable);
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ROM_uDMAChannelAssign(UDMA_CH11_SSI0TX);
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ROM_uDMAChannelAssign(UDMA_CH25_SSI1TX);
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ROM_uDMAChannelAssign(UDMA_CH13_SSI2TX);
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ROM_uDMAChannelAssign(UDMA_CH15_SSI3TX);
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uDMAChannelAssign(UDMA_CH11_SSI0TX);
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uDMAChannelAssign(UDMA_CH25_SSI1TX);
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uDMAChannelAssign(UDMA_CH13_SSI2TX);
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uDMAChannelAssign(UDMA_CH15_SSI3TX);
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ssi_udma_channel_config(11);
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ssi_udma_channel_config(25);
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ssi_udma_channel_config(13);
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ssi_udma_channel_config(15);
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ROM_SSIDMAEnable(SSI0_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI2_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX);
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SSIDMAEnable(SSI0_BASE, SSI_DMA_TX);
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SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
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SSIDMAEnable(SSI2_BASE, SSI_DMA_TX);
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SSIDMAEnable(SSI3_BASE, SSI_DMA_TX);
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ROM_IntEnable(INT_SSI0);
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IntEnable(INT_SSI0);
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/* Enable the SSIs after configuring anything around them. */
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ROM_SSIEnable(SSI0_BASE);
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ROM_SSIEnable(SSI1_BASE);
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ROM_SSIEnable(SSI2_BASE);
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ROM_SSIEnable(SSI3_BASE);
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SSIEnable(SSI0_BASE);
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SSIEnable(SSI1_BASE);
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SSIEnable(SSI2_BASE);
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SSIEnable(SSI3_BASE);
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UARTprintf("Booted.\n");
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