Basic DMA working
This commit is contained in:
jaseg
parent
f41dae78f8
commit
75106e9eb6
1 changed files with 139 additions and 110 deletions
249
firmware/main.c
249
firmware/main.c
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@ -64,14 +64,15 @@ unsigned const char const CRATE_MAP[CRATES_PER_BUS] = {
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7, 5, 3, 1
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};
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#define SYSTICKS_PER_SECOND 100
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#define SYSTICK_PERIOD_MS (1000 / SYSTICKS_PER_SECOND)
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#define SYSTICKS_PER_SECOND 100
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#define SYSTICK_PERIOD_MS (1000 / SYSTICKS_PER_SECOND)
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unsigned char framebuffer[BUS_COUNT*BUS_SIZE];
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/* Kick off DMA from RAM to SPI interfaces */
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void start_dma(void);
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unsigned long framebuffer_read(void *data, unsigned long len);
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void ssi_udma_channel_config(unsigned char channel, unsigned char offset);
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/* Kick off DMA transfer from RAM to SPI interfaces */
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void kickoff_transfers(void);
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void kickoff_transfer(unsigned int channel, unsigned int offset);
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void ssi_udma_channel_config(unsigned int channel);
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unsigned char ucControlTable[1024] __attribute__ ((aligned(1024)));
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@ -94,31 +95,39 @@ volatile unsigned long g_ulFlags = 0;
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char *g_pcStatus;
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static volatile tBoolean g_bUSBConfigured = false;
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void SysTickIntHandler(void){
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g_ulSysTickCount++;
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void SysTickIntHandler(void) {
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g_ulSysTickCount++;
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}
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/* Will be called when a DMA transfer is complete */
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void SSI0IntHandler(void) {
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if(!ROM_uDMAChannelIsEnabled(11)){
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/* A TX DMA transfer was completed */
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/* FIXME */
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}
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}
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unsigned long RxHandler(void *pvCBData, unsigned long ulEvent, unsigned long ulMsgValue, void *pvMsgData) {
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switch(ulEvent) {
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case USB_EVENT_CONNECTED:
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g_bUSBConfigured = true;
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UARTprintf("Host connected.\n");
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USBBufferFlush(&g_sRxBuffer);
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break;
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case USB_EVENT_DISCONNECTED:
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g_bUSBConfigured = false;
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UARTprintf("Host disconnected.\n");
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break;
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case USB_EVENT_RX_AVAILABLE:
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switch(ulEvent) {
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case USB_EVENT_CONNECTED:
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g_bUSBConfigured = true;
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UARTprintf("Host connected.\n");
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USBBufferFlush(&g_sRxBuffer);
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break;
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case USB_EVENT_DISCONNECTED:
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g_bUSBConfigured = false;
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UARTprintf("Host disconnected.\n");
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break;
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case USB_EVENT_RX_AVAILABLE:
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UARTprintf("Handling host data.\n");
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USBBufferDataRemoved(&g_sRxBuffer, framebuffer_read(pvMsgData, ulMsgValue));
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case USB_EVENT_SUSPEND:
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case USB_EVENT_RESUME:
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break;
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default:
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break;
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}
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return 0;
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case USB_EVENT_SUSPEND:
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case USB_EVENT_RESUME:
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break;
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default:
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break;
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}
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return 0;
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}
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typedef struct {
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@ -127,143 +136,163 @@ typedef struct {
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unsigned char rgb_data[CRATE_SIZE*BYTES_PER_PIXEL];
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} FramebufferData;
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unsigned long framebuffer_read(void *data, unsigned long len){
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unsigned long framebuffer_read(void *data, unsigned long len) {
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if(len != sizeof(FramebufferData))
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return len;
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UARTprintf("Rearranging data.\n");
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FramebufferData *fb = (FramebufferData *)data;
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unsigned int bus = fb->crate_x/4;
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unsigned int bus = fb->crate_x/CRATES_X;
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fb->crate_x %= CRATES_X;
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if(bus > BUS_COUNT || fb->crate_y > CRATES_Y){
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UARTprintf("Invalid frame index\n");
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return len;
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}
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/* Mirror crate map for the display's right half */
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if(bus >= BUS_COUNT/2)
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fb->crate_x = CRATES_X - fb->crate_x - 1;
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for(unsigned int x=0; x<CRATE_WIDTH; x++){
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for(unsigned int y=0; y<CRATE_HEIGHT; y++){
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unsigned int crate = CRATE_MAP[fb->crate_x + fb->crate_y*CRATES_X];
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unsigned int crate = CRATE_MAP[fb->crate_x + fb->crate_y*CRATES_X];
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unsigned int bottle = BOTTLE_MAP[x%CRATE_WIDTH + (y%CRATE_HEIGHT)*CRATE_WIDTH];
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unsigned int src = (bus*BUS_SIZE + crate*CRATE_SIZE + bottle)*3;
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unsigned int src = (bus*BUS_SIZE + crate*CRATE_SIZE + bottle)*3;
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unsigned int dst = (bus*BUS_SIZE + y*BUS_COLUMNS + x)*3;
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//Copy r, g and b data
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framebuffer[src] = fb->rgb_data[dst];
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/* Copy r, g and b data */
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framebuffer[src] = fb->rgb_data[dst];
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framebuffer[src + 1] = fb->rgb_data[dst + 1];
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framebuffer[src + 2] = fb->rgb_data[dst + 2];
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}
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}
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UARTprintf("Starting DMA.\n");
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start_dma();
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kickoff_transfers();
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return len;
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}
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void start_dma(void){
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void kickoff_transfers() {
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kickoff_transfer(11, 0);
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/* kickoff_transfer(25, 1);
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kickoff_transfer(13, 2);
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kickoff_transfer(15, 3); */
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}
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void ssi_udma_channel_config(unsigned char channel, unsigned char offset){
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/* Set the USEBURST attribute for the uDMA SSI TX channel. This will force the controller to always use a burst
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void kickoff_transfer(unsigned int channel, unsigned int offset) {
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ROM_uDMAChannelTransferSet(channel | UDMA_PRI_SELECT, UDMA_MODE_BASIC, framebuffer+BUS_SIZE*offset, (void *)(SSI0_BASE + SSI_O_DR), BUS_SIZE);
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ROM_uDMAChannelEnable(channel);
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}
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void ssi_udma_channel_config(unsigned int channel) {
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/* Set the USEBURST attribute for the uDMA SSI TX channel. This will force the controller to always use a burst
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* when transferring data from the TX buffer to the SSI. This is somewhat more effecient bus usage than the default
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* which allows single or burst transfers. */
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ROM_uDMAChannelAttributeEnable(channel, UDMA_ATTR_USEBURST);
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ROM_uDMAChannelAttributeEnable(channel, UDMA_ATTR_USEBURST);
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/* Configure the SSI Tx µDMA Channel to transfer from RAM to TX FIFO. The arbitration size is set to 4, which
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* matches the SSI TX FIFO µDMA trigger threshold. */
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ROM_uDMAChannelControlSet(channel, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4);
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ROM_uDMAChannelTransferSet(channel | UDMA_PRI_SELECT, UDMA_MODE_BASIC, framebuffer+BUS_SIZE*offset, (void *)(SSI0_BASE + SSI_O_DR), BUS_SIZE);
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ROM_uDMAChannelEnable(channel);
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ROM_uDMAChannelControlSet(channel | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4);
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}
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int main(void){
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int main(void) {
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/* Enable lazy stacking for interrupt handlers. This allows floating-point instructions to be used within interrupt
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* handlers, but at the expense of extra stack usage. */
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ROM_FPULazyStackingEnable();
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ROM_FPULazyStackingEnable();
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//Set clock to PLL at 50MHz
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
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SYSCTL_XTAL_16MHZ);
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/* Set clock to PLL at 50MHz */
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
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SYSCTL_XTAL_16MHZ);
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//Configure UART0 pins
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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GPIOPinConfigure(GPIO_PA0_U0RX);
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GPIOPinConfigure(GPIO_PA1_U0TX);
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ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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/* Configure UART0 pins */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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GPIOPinConfigure(GPIO_PA0_U0RX);
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GPIOPinConfigure(GPIO_PA1_U0TX);
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ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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//Enable the GPIO pins for the LED (PF2 & PF3).
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3|GPIO_PIN_2);
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/* Enable the GPIO pins for the LED (PF2 & PF3). */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3|GPIO_PIN_2);
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UARTStdioInit(0);
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UARTprintf("Booting...\n\n");
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UARTStdioInit(0);
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UARTprintf("Booting...\n\n");
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g_bUSBConfigured = false;
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g_bUSBConfigured = false;
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//Enable the GPIO peripheral used for USB, and configure the USB pins.
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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ROM_GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5);
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/* Enable the GPIO peripheral used for USB, and configure the USB pins. */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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ROM_GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5);
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//Enable the system tick.
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ROM_SysTickPeriodSet(ROM_SysCtlClockGet() / SYSTICKS_PER_SECOND);
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ROM_SysTickIntEnable();
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ROM_SysTickEnable();
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/* Enable the system tick. FIXME do we need this? */
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ROM_SysTickPeriodSet(ROM_SysCtlClockGet() / SYSTICKS_PER_SECOND);
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ROM_SysTickIntEnable();
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ROM_SysTickEnable();
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//Configure USB
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USBBufferInit((tUSBBuffer *)&g_sRxBuffer);
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USBStackModeSet(0, USB_MODE_FORCE_DEVICE, 0);
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USBDBulkInit(0, (tUSBDBulkDevice *)&g_sBulkDevice);
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/* Configure USB */
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USBBufferInit((tUSBBuffer *)&g_sRxBuffer);
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USBStackModeSet(0, USB_MODE_FORCE_DEVICE, 0);
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USBDBulkInit(0, (tUSBDBulkDevice *)&g_sBulkDevice);
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//Configure SSI0..3 for the ws2801's SPI-like protocol
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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GPIOPinConfigure(GPIO_PA2_SSI0CLK);
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GPIOPinConfigure(GPIO_PA5_SSI0TX);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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GPIOPinConfigure(GPIO_PA2_SSI0CLK);
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GPIOPinConfigure(GPIO_PA5_SSI0TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_5);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
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GPIOPinConfigure(GPIO_PB4_SSI2CLK);
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GPIOPinConfigure(GPIO_PB7_SSI2TX);
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/* Configure SSI0..3 for the ws2801's SPI-like protocol */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
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/* ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); */
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/* ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
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GPIOPinConfigure(GPIO_PB4_SSI2CLK);
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GPIOPinConfigure(GPIO_PB7_SSI2TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_7);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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GPIOPinConfigure(GPIO_PD0_SSI3CLK);
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GPIOPinConfigure(GPIO_PD3_SSI3TX);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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GPIOPinConfigure(GPIO_PD0_SSI3CLK);
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GPIOPinConfigure(GPIO_PD3_SSI3TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_3);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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GPIOPinConfigure(GPIO_PF2_SSI1CLK);
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GPIOPinConfigure(GPIO_PF1_SSI1TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_3);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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GPIOPinConfigure(GPIO_PF2_SSI1CLK);
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GPIOPinConfigure(GPIO_PF1_SSI1TX);
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ROM_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_3); */
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SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8);
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SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8);
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SSIConfigSetExpClk(SSI2_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8);
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SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8);
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/* 200kBd */
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SSIConfigSetExpClk(SSI0_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 200000, 8);
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/* SSIConfigSetExpClk(SSI1_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 200000, 8);
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SSIConfigSetExpClk(SSI2_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 200000, 8);
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SSIConfigSetExpClk(SSI3_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 200000, 8); */
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//Configure the µDMA controller for use by the SPI interface
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
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ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
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ROM_IntEnable(INT_UDMAERR); // Enable µDMA error interrupt
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ROM_uDMAEnable();
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ROM_uDMAControlBaseSet(ucControlTable);
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/* Configure the µDMA controller for use by the SPI interface */
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
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ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
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ROM_IntEnable(INT_UDMAERR); // Enable µDMA error interrupt
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ROM_uDMAEnable();
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ROM_uDMAControlBaseSet(ucControlTable);
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ROM_uDMAChannelAssign(UDMA_CH11_SSI0TX);
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ROM_uDMAChannelAssign(UDMA_CH25_SSI1TX);
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/* ROM_uDMAChannelAssign(UDMA_CH25_SSI1TX);
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ROM_uDMAChannelAssign(UDMA_CH13_SSI2TX);
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ROM_uDMAChannelAssign(UDMA_CH15_SSI3TX);
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ROM_uDMAChannelAssign(UDMA_CH15_SSI3TX); */
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ssi_udma_channel_config(11, 0);
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ssi_udma_channel_config(25, 1);
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ssi_udma_channel_config(13, 2);
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ssi_udma_channel_config(15, 3);
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ssi_udma_channel_config(11);
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/* ssi_udma_channel_config(25);
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ssi_udma_channel_config(13);
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ssi_udma_channel_config(15); */
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ROM_SSIDMAEnable(SSI0_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
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/* ROM_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI2_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX);
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ROM_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX); */
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//Enable the SSIs after configuring anything around them.
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SSIEnable(SSI0_BASE);
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SSIEnable(SSI1_BASE);
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SSIEnable(SSI2_BASE);
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SSIEnable(SSI3_BASE);
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/* Enable the SSIs after configuring anything around them. */
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ROM_SSIEnable(SSI0_BASE);
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/* ROM_SSIEnable(SSI1_BASE);
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ROM_SSIEnable(SSI2_BASE);
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ROM_SSIEnable(SSI3_BASE); */
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UARTprintf("Booted.\n");
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while(1){
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}
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while(1);
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}
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