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master-thesis/gm_platform/fw/main.lst
jaseg f4a6ea896f serial basically working
2020-01-27 21:58:22 +01:00

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main.elf: file format elf32-littlearm
SYMBOL TABLE:
08000000 l d .isr_vector 00000000 .isr_vector
080000c0 l d .text 00000000 .text
20000000 l d .data 00000000 .data
20000094 l d .bss 00000000 .bss
00000000 l d .comment 00000000 .comment
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l df *ABS* 00000000 /tmp/ccjaIjJQ.o
08001c0c l .text 00000000 LoopCopyDataInit
08001c04 l .text 00000000 CopyDataInit
08001c20 l .text 00000000 LoopFillZerobss
08001c1a l .text 00000000 FillZerobss
08001c2e l .text 00000000 LoopForever
08001c48 l .text 00000000 Infinite_Loop
00000000 l df *ABS* 00000000 main.c
080000c0 l F .text 0000002c NVIC_EnableIRQ
080000ec l F .text 000000dc NVIC_SetPriority
080001c8 l F .text 00000048 SysTick_Config
20000098 l .bss 00000004 leds_update_counter.5792
2000009c l .bss 00000004 n.5815
00000000 l df *ABS* 00000000 adc.c
080004e8 l F .text 0000002c NVIC_EnableIRQ
08000514 l F .text 000000dc NVIC_SetPriority
200000a0 l .bss 00000090 adc_pkt
20000130 l .bss 00000002 current_seq
20000134 l .bss 00000004 current_buf
08000690 l F .text 00000040 adc_dma_init
0800072c l F .text 00000064 adc_timer_init
080006d0 l F .text 0000005c adc_dma_launch
08000790 l F .text 0000000a gdb_dump
00000000 l df *ABS* 00000000 serial.c
0800081c l F .text 0000002c NVIC_EnableIRQ
08000848 l F .text 00000030 NVIC_DisableIRQ
08000878 l F .text 000000dc NVIC_SetPriority
20000138 l .bss 00000004 tx_overruns
2000013c l .bss 00000004 rx_overruns
20000140 l .bss 00000004 rx_framing_errors
20000144 l .bss 00000004 rx_protocol_errors
20000148 l .bss 00000008 cobs_state
20000150 l .bss 00000020 rx_buf
08000d10 l F .text 000000ac usart_retransmit_packet
08000b50 l F .text 00000074 usart_schedule_dma
08000ca8 l F .text 00000028 usart_putc_nonblocking
00000000 l df *ABS* 00000000 cobs.c
00000000 l df *ABS* 00000000 system_stm32f0xx.c
00000000 l df *ABS* 00000000 stm32f0xx_ll_utils.c
080012f8 l F .text 0000001c LL_RCC_HSE_EnableBypass
08001314 l F .text 00000020 LL_RCC_HSE_DisableBypass
08001334 l F .text 0000001c LL_RCC_HSE_Enable
08001350 l F .text 00000028 LL_RCC_HSE_IsReady
08001378 l F .text 0000001c LL_RCC_HSI_Enable
08001394 l F .text 00000020 LL_RCC_HSI_IsReady
080013b4 l F .text 00000028 LL_RCC_SetSysClkSource
080013dc l F .text 00000018 LL_RCC_GetSysClkSource
080013f4 l F .text 00000028 LL_RCC_SetAHBPrescaler
0800141c l F .text 0000002c LL_RCC_SetAPB1Prescaler
08001448 l F .text 0000001c LL_RCC_PLL_Enable
08001464 l F .text 00000028 LL_RCC_PLL_IsReady
0800148c l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
080014d8 l F .text 00000034 LL_InitTick
0800150c l F .text 00000028 LL_FLASH_SetLatency
08001534 l F .text 00000018 LL_FLASH_GetLatency
0800178e l F .text 00000026 UTILS_PLL_IsBusy
08001754 l F .text 0000003a UTILS_GetPLLOutputFrequency
080017b4 l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
080016f8 l F .text 0000005c UTILS_SetFlashLatency
00000000 l df *ABS* 00000000 base.c
00000000 l df *ABS* 00000000 cmsis_exports.c
00000000 l df *ABS* 00000000 _udivsi3.o
08001910 l .text 00000000 .udivsi3_skip_div0_test
00000000 l df *ABS* 00000000 _divsi3.o
08001a24 l .text 00000000 .divsi3_skip_div0_test
00000000 l df *ABS* 00000000 _dvmd_tls.o
08001c5c g O .text 00000008 APBPrescTable
20000044 g O .data 00000004 tim17
2000007c g O .data 00000004 gpioc
20000088 g O .data 00000004 scb
0800156a g F .text 00000046 LL_mDelay
08001c48 w F .text 00000002 TIM1_CC_IRQHandler
0800188c g F .text 0000000a __sinit
08000490 g F .text 00000004 HardFault_Handler
2000006c g O .data 00000004 rcc
080004ac g F .text 0000003c SysTick_Handler
08001c64 g .text 00000000 _sidata
080004a0 g F .text 0000000c PendSV_Handler
20000020 g O .data 00000004 syscfg
08000484 g F .text 0000000c NMI_Handler
200003b8 g .bss 00000000 __exidx_end
080015cc g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
08001c48 w F .text 00000002 I2C1_IRQHandler
080015b0 g F .text 0000001c LL_SetSystemCoreClock
20000170 g O .bss 00000004 __errno
20000008 g O .data 00000004 tim14
20000048 g O .data 00000004 dbgmcu
2000003c g O .data 00000004 usart1
08001c64 g .text 00000000 _etext
20000094 g .bss 00000000 _sbss
08000f9a g F .text 000000d6 cobs_decode
20000198 g O .bss 00000220 usart_tx_buf
20000094 g O .bss 00000004 sys_time_seconds
20000000 g O .data 00000004 SystemCoreClock
2000001c g O .data 00000004 pwr
08001910 g F .text 0000010a .hidden __udivsi3
080018fa g F .text 00000014 __assert_func
20000000 g .data 00000000 _sdata
0800039c g F .text 0000002c SPI1_IRQHandler
20000060 g O .data 00000004 dma1_channel5
20000058 g O .data 00000004 dma1_channel3
200003b8 g .bss 00000000 __exidx_start
0800154c g F .text 0000001e LL_Init1msTick
20000054 g O .data 00000004 dma1_channel2
08001c48 w F .text 00000002 EXTI2_3_IRQHandler
08001c48 w F .text 00000002 ADC1_IRQHandler
0800108c g F .text 000000e2 cobs_decode_incremental
2000004c g O .data 00000004 dma1
08001c48 w F .text 00000002 TIM17_IRQHandler
08001c48 w F .text 00000002 RTC_IRQHandler
200003b8 g .bss 00000000 _ebss
2000002c g O .data 00000004 adc1_common
08001bfc w F .text 00000034 Reset_Handler
20000070 g O .data 00000004 crc
20000024 g O .data 00000004 exti
08000210 g F .text 0000000a update_leds
20000028 g O .data 00000004 adc1
08001a24 g F .text 00000000 .hidden __aeabi_idiv
20000178 g O .bss 00000020 leds
20000074 g O .data 00000004 gpioa
080003c8 g F .text 000000bc TIM16_IRQHandler
08001c48 w F .text 00000002 TIM3_IRQHandler
08001c48 w F .text 00000002 EXTI4_15_IRQHandler
08001c48 w F .text 00000002 RCC_IRQHandler
08000dbc g F .text 00000120 usart_send_packet_nonblocking
20000094 g .bss 00000000 _bss
0800079a g F .text 00000082 DMA1_Channel1_IRQHandler
08001c48 g .text 00000002 Default_Handler
08001c4c g O .text 00000010 AHBPrescTable
08000edc g F .text 000000be cobs_encode_usart
20000010 g O .data 00000004 wwdg
08001c48 w F .text 00000002 TIM14_IRQHandler
08001c48 w F .text 00000002 DMA1_Channel4_5_IRQHandler
20000030 g O .data 00000004 adc
08000c78 g F .text 00000030 usart_putc
08001c48 w F .text 00000002 EXTI0_1_IRQHandler
08001bf8 w F .text 00000002 .hidden __aeabi_ldiv0
20000004 g O .data 00000004 tim3
2000000c g O .data 00000004 rtc
08000954 g F .text 000000d4 usart_dma_init
08001896 g F .text 0000003a memset
08000bc4 g F .text 0000003c usart_ack_packet
0800021a g F .text 00000182 main
20000064 g O .data 00000004 flash
08001910 g F .text 00000000 .hidden __aeabi_uidiv
08000494 g F .text 0000000c SVC_Handler
20000018 g O .data 00000004 i2c1
20000050 g O .data 00000004 dma1_channel1
08001a24 g F .text 000001cc .hidden __divsi3
20000090 g O .data 00000004 nvic
08001184 g F .text 00000088 SystemInit
20000174 g O .bss 00000004 _impure_ptr
08001c48 w F .text 00000002 WWDG_IRQHandler
20000000 g .data 00000000 _data
20000084 g O .data 00000004 gpiof
08000cd0 g F .text 00000040 DMA1_Channel2_3_IRQHandler
20000080 g O .data 00000004 gpiod
20001000 g *ABS* 00000000 _estack
08001a1c g F .text 00000008 .hidden __aeabi_uidivmod
20000068 g O .data 00000004 ob
20000094 g .data 00000000 _edata
20000038 g O .data 00000004 spi1
08000c00 g F .text 00000078 usart_dma_fifo_push
2000005c g O .data 00000004 dma1_channel4
08000000 g O .isr_vector 00000000 g_pfnVectors
0800120c g F .text 000000ec SystemCoreClockUpdate
08001658 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
08001bf8 w F .text 00000002 .hidden __aeabi_idiv0
20000014 g O .data 00000004 iwdg
08001c48 w F .text 00000002 FLASH_IRQHandler
08001070 g F .text 0000001c cobs_decode_incremental_initialize
08000a28 g F .text 00000128 USART1_IRQHandler
080005f0 g F .text 000000a0 adc_configure_scope_mode
080018d0 g F .text 0000002a strlen
08001c48 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
20000078 g O .data 00000004 gpiob
20000034 g O .data 00000004 tim1
2000008c g O .data 00000004 systick
08001bf0 g F .text 00000008 .hidden __aeabi_idivmod
20000040 g O .data 00000004 tim16
Disassembly of section .text:
080000c0 <NVIC_EnableIRQ>:
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
80000c0: b580 push {r7, lr}
80000c2: b082 sub sp, #8
80000c4: af00 add r7, sp, #0
80000c6: 0002 movs r2, r0
80000c8: 1dfb adds r3, r7, #7
80000ca: 701a strb r2, [r3, #0]
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
80000cc: 1dfb adds r3, r7, #7
80000ce: 781b ldrb r3, [r3, #0]
80000d0: 001a movs r2, r3
80000d2: 231f movs r3, #31
80000d4: 401a ands r2, r3
80000d6: 4b04 ldr r3, [pc, #16] ; (80000e8 <NVIC_EnableIRQ+0x28>)
80000d8: 2101 movs r1, #1
80000da: 4091 lsls r1, r2
80000dc: 000a movs r2, r1
80000de: 601a str r2, [r3, #0]
}
80000e0: 46c0 nop ; (mov r8, r8)
80000e2: 46bd mov sp, r7
80000e4: b002 add sp, #8
80000e6: bd80 pop {r7, pc}
80000e8: e000e100 .word 0xe000e100
080000ec <NVIC_SetPriority>:
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80000ec: b590 push {r4, r7, lr}
80000ee: b083 sub sp, #12
80000f0: af00 add r7, sp, #0
80000f2: 0002 movs r2, r0
80000f4: 6039 str r1, [r7, #0]
80000f6: 1dfb adds r3, r7, #7
80000f8: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) < 0)
80000fa: 1dfb adds r3, r7, #7
80000fc: 781b ldrb r3, [r3, #0]
80000fe: 2b7f cmp r3, #127 ; 0x7f
8000100: d932 bls.n 8000168 <NVIC_SetPriority+0x7c>
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000102: 4a2f ldr r2, [pc, #188] ; (80001c0 <NVIC_SetPriority+0xd4>)
8000104: 1dfb adds r3, r7, #7
8000106: 781b ldrb r3, [r3, #0]
8000108: 0019 movs r1, r3
800010a: 230f movs r3, #15
800010c: 400b ands r3, r1
800010e: 3b08 subs r3, #8
8000110: 089b lsrs r3, r3, #2
8000112: 3306 adds r3, #6
8000114: 009b lsls r3, r3, #2
8000116: 18d3 adds r3, r2, r3
8000118: 3304 adds r3, #4
800011a: 681b ldr r3, [r3, #0]
800011c: 1dfa adds r2, r7, #7
800011e: 7812 ldrb r2, [r2, #0]
8000120: 0011 movs r1, r2
8000122: 2203 movs r2, #3
8000124: 400a ands r2, r1
8000126: 00d2 lsls r2, r2, #3
8000128: 21ff movs r1, #255 ; 0xff
800012a: 4091 lsls r1, r2
800012c: 000a movs r2, r1
800012e: 43d2 mvns r2, r2
8000130: 401a ands r2, r3
8000132: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000134: 683b ldr r3, [r7, #0]
8000136: 019b lsls r3, r3, #6
8000138: 22ff movs r2, #255 ; 0xff
800013a: 401a ands r2, r3
800013c: 1dfb adds r3, r7, #7
800013e: 781b ldrb r3, [r3, #0]
8000140: 0018 movs r0, r3
8000142: 2303 movs r3, #3
8000144: 4003 ands r3, r0
8000146: 00db lsls r3, r3, #3
8000148: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800014a: 481d ldr r0, [pc, #116] ; (80001c0 <NVIC_SetPriority+0xd4>)
800014c: 1dfb adds r3, r7, #7
800014e: 781b ldrb r3, [r3, #0]
8000150: 001c movs r4, r3
8000152: 230f movs r3, #15
8000154: 4023 ands r3, r4
8000156: 3b08 subs r3, #8
8000158: 089b lsrs r3, r3, #2
800015a: 430a orrs r2, r1
800015c: 3306 adds r3, #6
800015e: 009b lsls r3, r3, #2
8000160: 18c3 adds r3, r0, r3
8000162: 3304 adds r3, #4
8000164: 601a str r2, [r3, #0]
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8000166: e027 b.n 80001b8 <NVIC_SetPriority+0xcc>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000168: 4a16 ldr r2, [pc, #88] ; (80001c4 <NVIC_SetPriority+0xd8>)
800016a: 1dfb adds r3, r7, #7
800016c: 781b ldrb r3, [r3, #0]
800016e: b25b sxtb r3, r3
8000170: 089b lsrs r3, r3, #2
8000172: 33c0 adds r3, #192 ; 0xc0
8000174: 009b lsls r3, r3, #2
8000176: 589b ldr r3, [r3, r2]
8000178: 1dfa adds r2, r7, #7
800017a: 7812 ldrb r2, [r2, #0]
800017c: 0011 movs r1, r2
800017e: 2203 movs r2, #3
8000180: 400a ands r2, r1
8000182: 00d2 lsls r2, r2, #3
8000184: 21ff movs r1, #255 ; 0xff
8000186: 4091 lsls r1, r2
8000188: 000a movs r2, r1
800018a: 43d2 mvns r2, r2
800018c: 401a ands r2, r3
800018e: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8000190: 683b ldr r3, [r7, #0]
8000192: 019b lsls r3, r3, #6
8000194: 22ff movs r2, #255 ; 0xff
8000196: 401a ands r2, r3
8000198: 1dfb adds r3, r7, #7
800019a: 781b ldrb r3, [r3, #0]
800019c: 0018 movs r0, r3
800019e: 2303 movs r3, #3
80001a0: 4003 ands r3, r0
80001a2: 00db lsls r3, r3, #3
80001a4: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80001a6: 4807 ldr r0, [pc, #28] ; (80001c4 <NVIC_SetPriority+0xd8>)
80001a8: 1dfb adds r3, r7, #7
80001aa: 781b ldrb r3, [r3, #0]
80001ac: b25b sxtb r3, r3
80001ae: 089b lsrs r3, r3, #2
80001b0: 430a orrs r2, r1
80001b2: 33c0 adds r3, #192 ; 0xc0
80001b4: 009b lsls r3, r3, #2
80001b6: 501a str r2, [r3, r0]
}
80001b8: 46c0 nop ; (mov r8, r8)
80001ba: 46bd mov sp, r7
80001bc: b003 add sp, #12
80001be: bd90 pop {r4, r7, pc}
80001c0: e000ed00 .word 0xe000ed00
80001c4: e000e100 .word 0xe000e100
080001c8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80001c8: b580 push {r7, lr}
80001ca: b082 sub sp, #8
80001cc: af00 add r7, sp, #0
80001ce: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80001d0: 687b ldr r3, [r7, #4]
80001d2: 1e5a subs r2, r3, #1
80001d4: 2380 movs r3, #128 ; 0x80
80001d6: 045b lsls r3, r3, #17
80001d8: 429a cmp r2, r3
80001da: d301 bcc.n 80001e0 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
80001dc: 2301 movs r3, #1
80001de: e010 b.n 8000202 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80001e0: 4b0a ldr r3, [pc, #40] ; (800020c <SysTick_Config+0x44>)
80001e2: 687a ldr r2, [r7, #4]
80001e4: 3a01 subs r2, #1
80001e6: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80001e8: 2301 movs r3, #1
80001ea: 425b negs r3, r3
80001ec: 2103 movs r1, #3
80001ee: 0018 movs r0, r3
80001f0: f7ff ff7c bl 80000ec <NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80001f4: 4b05 ldr r3, [pc, #20] ; (800020c <SysTick_Config+0x44>)
80001f6: 2200 movs r2, #0
80001f8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80001fa: 4b04 ldr r3, [pc, #16] ; (800020c <SysTick_Config+0x44>)
80001fc: 2207 movs r2, #7
80001fe: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000200: 2300 movs r3, #0
}
8000202: 0018 movs r0, r3
8000204: 46bd mov sp, r7
8000206: b002 add sp, #8
8000208: bd80 pop {r7, pc}
800020a: 46c0 nop ; (mov r8, r8)
800020c: e000e010 .word 0xe000e010
08000210 <update_leds>:
#include "serial.h"
volatile unsigned int sys_time_seconds = 0;
void update_leds() {
8000210: b580 push {r7, lr}
8000212: af00 add r7, sp, #0
}
8000214: 46c0 nop ; (mov r8, r8)
8000216: 46bd mov sp, r7
8000218: bd80 pop {r7, pc}
0800021a <main>:
unsigned int usb, ocxo, error, _nc1, _nc2, _nc3, pps, sd_card;
};
unsigned int arr[8];
} leds;
int main(void) {
800021a: b580 push {r7, lr}
800021c: af00 add r7, sp, #0
RCC->CR |= RCC_CR_HSEON;
800021e: 4b53 ldr r3, [pc, #332] ; (800036c <main+0x152>)
8000220: 681a ldr r2, [r3, #0]
8000222: 4b52 ldr r3, [pc, #328] ; (800036c <main+0x152>)
8000224: 2180 movs r1, #128 ; 0x80
8000226: 0249 lsls r1, r1, #9
8000228: 430a orrs r2, r1
800022a: 601a str r2, [r3, #0]
while (!(RCC->CR&RCC_CR_HSERDY));
800022c: 46c0 nop ; (mov r8, r8)
800022e: 4b4f ldr r3, [pc, #316] ; (800036c <main+0x152>)
8000230: 681a ldr r2, [r3, #0]
8000232: 2380 movs r3, #128 ; 0x80
8000234: 029b lsls r3, r3, #10
8000236: 4013 ands r3, r2
8000238: d0f9 beq.n 800022e <main+0x14>
RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
800023a: 4b4c ldr r3, [pc, #304] ; (800036c <main+0x152>)
800023c: 685a ldr r2, [r3, #4]
800023e: 4b4b ldr r3, [pc, #300] ; (800036c <main+0x152>)
8000240: 494b ldr r1, [pc, #300] ; (8000370 <main+0x156>)
8000242: 400a ands r2, r1
8000244: 605a str r2, [r3, #4]
RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */
8000246: 4b49 ldr r3, [pc, #292] ; (800036c <main+0x152>)
8000248: 685a ldr r2, [r3, #4]
800024a: 4b48 ldr r3, [pc, #288] ; (800036c <main+0x152>)
800024c: 2188 movs r1, #136 ; 0x88
800024e: 0349 lsls r1, r1, #13
8000250: 430a orrs r2, r1
8000252: 605a str r2, [r3, #4]
RCC->CR |= RCC_CR_PLLON;
8000254: 4b45 ldr r3, [pc, #276] ; (800036c <main+0x152>)
8000256: 681a ldr r2, [r3, #0]
8000258: 4b44 ldr r3, [pc, #272] ; (800036c <main+0x152>)
800025a: 2180 movs r1, #128 ; 0x80
800025c: 0449 lsls r1, r1, #17
800025e: 430a orrs r2, r1
8000260: 601a str r2, [r3, #0]
while (!(RCC->CR&RCC_CR_PLLRDY));
8000262: 46c0 nop ; (mov r8, r8)
8000264: 4b41 ldr r3, [pc, #260] ; (800036c <main+0x152>)
8000266: 681a ldr r2, [r3, #0]
8000268: 2380 movs r3, #128 ; 0x80
800026a: 049b lsls r3, r3, #18
800026c: 4013 ands r3, r2
800026e: d0f9 beq.n 8000264 <main+0x4a>
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
8000270: 4b3e ldr r3, [pc, #248] ; (800036c <main+0x152>)
8000272: 685a ldr r2, [r3, #4]
8000274: 4b3d ldr r3, [pc, #244] ; (800036c <main+0x152>)
8000276: 2102 movs r1, #2
8000278: 430a orrs r2, r1
800027a: 605a str r2, [r3, #4]
SystemCoreClockUpdate();
800027c: f000 ffc6 bl 800120c <SystemCoreClockUpdate>
SysTick_Config(SystemCoreClock/10); /* 100ms interval */
8000280: 4b3c ldr r3, [pc, #240] ; (8000374 <main+0x15a>)
8000282: 681b ldr r3, [r3, #0]
8000284: 210a movs r1, #10
8000286: 0018 movs r0, r3
8000288: f001 fb42 bl 8001910 <__udivsi3>
800028c: 0003 movs r3, r0
800028e: 0018 movs r0, r3
8000290: f7ff ff9a bl 80001c8 <SysTick_Config>
NVIC_EnableIRQ(SysTick_IRQn);
8000294: 2301 movs r3, #1
8000296: 425b negs r3, r3
8000298: 0018 movs r0, r3
800029a: f7ff ff11 bl 80000c0 <NVIC_EnableIRQ>
NVIC_SetPriority(SysTick_IRQn, 3<<5);
800029e: 2301 movs r3, #1
80002a0: 425b negs r3, r3
80002a2: 2160 movs r1, #96 ; 0x60
80002a4: 0018 movs r0, r3
80002a6: f7ff ff21 bl 80000ec <NVIC_SetPriority>
/* Turn on lots of neat things */
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN | RCC_AHBENR_CRCEN;
80002aa: 4b30 ldr r3, [pc, #192] ; (800036c <main+0x152>)
80002ac: 695a ldr r2, [r3, #20]
80002ae: 4b2f ldr r3, [pc, #188] ; (800036c <main+0x152>)
80002b0: 4931 ldr r1, [pc, #196] ; (8000378 <main+0x15e>)
80002b2: 430a orrs r2, r1
80002b4: 615a str r2, [r3, #20]
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_DBGMCUEN |\
80002b6: 4b2d ldr r3, [pc, #180] ; (800036c <main+0x152>)
80002b8: 699a ldr r2, [r3, #24]
80002ba: 4b2c ldr r3, [pc, #176] ; (800036c <main+0x152>)
80002bc: 492f ldr r1, [pc, #188] ; (800037c <main+0x162>)
80002be: 430a orrs r2, r1
80002c0: 619a str r2, [r3, #24]
RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN | RCC_APB2ENR_USART1EN;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
80002c2: 4b2a ldr r3, [pc, #168] ; (800036c <main+0x152>)
80002c4: 69da ldr r2, [r3, #28]
80002c6: 4b29 ldr r3, [pc, #164] ; (800036c <main+0x152>)
80002c8: 2102 movs r1, #2
80002ca: 430a orrs r2, r1
80002cc: 61da str r2, [r3, #28]
GPIOA->MODER |=
80002ce: 2390 movs r3, #144 ; 0x90
80002d0: 05db lsls r3, r3, #23
80002d2: 681a ldr r2, [r3, #0]
80002d4: 2390 movs r3, #144 ; 0x90
80002d6: 05db lsls r3, r3, #23
80002d8: 4929 ldr r1, [pc, #164] ; (8000380 <main+0x166>)
80002da: 430a orrs r2, r1
80002dc: 601a str r2, [r3, #0]
| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
| (2<<GPIO_MODER_MODER9_Pos) /* PA9 - HOST_RX */
| (2<<GPIO_MODER_MODER10_Pos);/* PA10 - HOST_TX */
/* Set shift register IO GPIO output speed */
GPIOA->OSPEEDR |=
80002de: 2390 movs r3, #144 ; 0x90
80002e0: 05db lsls r3, r3, #23
80002e2: 689a ldr r2, [r3, #8]
80002e4: 2390 movs r3, #144 ; 0x90
80002e6: 05db lsls r3, r3, #23
80002e8: 4926 ldr r1, [pc, #152] ; (8000384 <main+0x16a>)
80002ea: 430a orrs r2, r1
80002ec: 609a str r2, [r3, #8]
| (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* SD_CS */
| (2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCK */
| (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */
| (2<<GPIO_OSPEEDR_OSPEEDR9_Pos); /* HOST_RX */
GPIOA->AFR[0] = (0<<GPIO_AFRL_AFRL5_Pos) | (0<<GPIO_AFRL_AFRL6_Pos) | (0<<GPIO_AFRL_AFRL7_Pos);
80002ee: 2390 movs r3, #144 ; 0x90
80002f0: 05db lsls r3, r3, #23
80002f2: 2200 movs r2, #0
80002f4: 621a str r2, [r3, #32]
GPIOA->AFR[1] = (1<<8) | (1<<4);
80002f6: 2390 movs r3, #144 ; 0x90
80002f8: 05db lsls r3, r3, #23
80002fa: 2288 movs r2, #136 ; 0x88
80002fc: 0052 lsls r2, r2, #1
80002fe: 625a str r2, [r3, #36] ; 0x24
GPIOB->MODER |=
8000300: 4a21 ldr r2, [pc, #132] ; (8000388 <main+0x16e>)
8000302: 4b21 ldr r3, [pc, #132] ; (8000388 <main+0x16e>)
8000304: 6812 ldr r2, [r2, #0]
8000306: 601a str r2, [r3, #0]
(0<<GPIO_MODER_MODER1_Pos); /* PB0 - LINE_POL */
SPI1->CR1 =
8000308: 4b20 ldr r3, [pc, #128] ; (800038c <main+0x172>)
800030a: 22c9 movs r2, #201 ; 0xc9
800030c: 0092 lsls r2, r2, #2
800030e: 601a str r2, [r3, #0]
SPI_CR1_SSM
| SPI_CR1_SSI
| (4<<SPI_CR1_BR_Pos) /* /32 ~1.5MHz */
| SPI_CR1_MSTR;
SPI1->CR2 = (7<<SPI_CR2_DS_Pos);
8000310: 4b1e ldr r3, [pc, #120] ; (800038c <main+0x172>)
8000312: 22e0 movs r2, #224 ; 0xe0
8000314: 00d2 lsls r2, r2, #3
8000316: 605a str r2, [r3, #4]
SPI1->CR1 |= SPI_CR1_SPE;
8000318: 4b1c ldr r3, [pc, #112] ; (800038c <main+0x172>)
800031a: 681a ldr r2, [r3, #0]
800031c: 4b1b ldr r3, [pc, #108] ; (800038c <main+0x172>)
800031e: 2140 movs r1, #64 ; 0x40
8000320: 430a orrs r2, r1
8000322: 601a str r2, [r3, #0]
NVIC_EnableIRQ(SPI1_IRQn);
8000324: 2019 movs r0, #25
8000326: f7ff fecb bl 80000c0 <NVIC_EnableIRQ>
NVIC_SetPriority(SPI1_IRQn, 2<<5);
800032a: 2140 movs r1, #64 ; 0x40
800032c: 2019 movs r0, #25
800032e: f7ff fedd bl 80000ec <NVIC_SetPriority>
TIM16->CR2 = 0;
8000332: 4b17 ldr r3, [pc, #92] ; (8000390 <main+0x176>)
8000334: 2200 movs r2, #0
8000336: 605a str r2, [r3, #4]
TIM16->DIER = TIM_DIER_UIE;
8000338: 4b15 ldr r3, [pc, #84] ; (8000390 <main+0x176>)
800033a: 2201 movs r2, #1
800033c: 60da str r2, [r3, #12]
TIM16->PSC = 48-1; /* 1us */
800033e: 4b14 ldr r3, [pc, #80] ; (8000390 <main+0x176>)
8000340: 222f movs r2, #47 ; 0x2f
8000342: 629a str r2, [r3, #40] ; 0x28
TIM16->ARR = 1000-1; /* 1ms */
8000344: 4b12 ldr r3, [pc, #72] ; (8000390 <main+0x176>)
8000346: 4a13 ldr r2, [pc, #76] ; (8000394 <main+0x17a>)
8000348: 62da str r2, [r3, #44] ; 0x2c
TIM16->CR1 = TIM_CR1_CEN;
800034a: 4b11 ldr r3, [pc, #68] ; (8000390 <main+0x176>)
800034c: 2201 movs r2, #1
800034e: 601a str r2, [r3, #0]
NVIC_EnableIRQ(TIM16_IRQn);
8000350: 2015 movs r0, #21
8000352: f7ff feb5 bl 80000c0 <NVIC_EnableIRQ>
NVIC_SetPriority(TIM16_IRQn, 2<<5);
8000356: 2140 movs r1, #64 ; 0x40
8000358: 2015 movs r0, #21
800035a: f7ff fec7 bl 80000ec <NVIC_SetPriority>
adc_configure_scope_mode(1000000);
800035e: 4b0e ldr r3, [pc, #56] ; (8000398 <main+0x17e>)
8000360: 0018 movs r0, r3
8000362: f000 f945 bl 80005f0 <adc_configure_scope_mode>
usart_dma_init();
8000366: f000 faf5 bl 8000954 <usart_dma_init>
while (42) {
800036a: e7fe b.n 800036a <main+0x150>
800036c: 40021000 .word 0x40021000
8000370: ffc3f80c .word 0xffc3f80c
8000374: 20000000 .word 0x20000000
8000378: 00060051 .word 0x00060051
800037c: 00425a01 .word 0x00425a01
8000380: 0028a970 .word 0x0028a970
8000384: 00088a80 .word 0x00088a80
8000388: 48000400 .word 0x48000400
800038c: 40013000 .word 0x40013000
8000390: 40014400 .word 0x40014400
8000394: 000003e7 .word 0x000003e7
8000398: 000f4240 .word 0x000f4240
0800039c <SPI1_IRQHandler>:
//for (int i=0; i<10000; i++) ;
//leds.error = 100;
}
}
void SPI1_IRQHandler(void) {
800039c: b580 push {r7, lr}
800039e: af00 add r7, sp, #0
if (SPI1->SR & SPI_SR_TXE) {
80003a0: 4b08 ldr r3, [pc, #32] ; (80003c4 <SPI1_IRQHandler+0x28>)
80003a2: 689b ldr r3, [r3, #8]
80003a4: 2202 movs r2, #2
80003a6: 4013 ands r3, r2
80003a8: d009 beq.n 80003be <SPI1_IRQHandler+0x22>
/* LED_STB */
GPIOA->BSRR = 1<<3;
80003aa: 2390 movs r3, #144 ; 0x90
80003ac: 05db lsls r3, r3, #23
80003ae: 2208 movs r2, #8
80003b0: 619a str r2, [r3, #24]
SPI1->CR2 &= ~SPI_CR2_TXEIE;
80003b2: 4b04 ldr r3, [pc, #16] ; (80003c4 <SPI1_IRQHandler+0x28>)
80003b4: 685a ldr r2, [r3, #4]
80003b6: 4b03 ldr r3, [pc, #12] ; (80003c4 <SPI1_IRQHandler+0x28>)
80003b8: 2180 movs r1, #128 ; 0x80
80003ba: 438a bics r2, r1
80003bc: 605a str r2, [r3, #4]
}
}
80003be: 46c0 nop ; (mov r8, r8)
80003c0: 46bd mov sp, r7
80003c2: bd80 pop {r7, pc}
80003c4: 40013000 .word 0x40013000
080003c8 <TIM16_IRQHandler>:
void TIM16_IRQHandler(void) {
80003c8: b580 push {r7, lr}
80003ca: b082 sub sp, #8
80003cc: af00 add r7, sp, #0
static int leds_update_counter = 0;
if (TIM16->SR & TIM_SR_UIF) {
80003ce: 4b28 ldr r3, [pc, #160] ; (8000470 <TIM16_IRQHandler+0xa8>)
80003d0: 691b ldr r3, [r3, #16]
80003d2: 2201 movs r2, #1
80003d4: 4013 ands r3, r2
80003d6: d047 beq.n 8000468 <TIM16_IRQHandler+0xa0>
TIM16->SR &= ~TIM_SR_UIF;
80003d8: 4b25 ldr r3, [pc, #148] ; (8000470 <TIM16_IRQHandler+0xa8>)
80003da: 691a ldr r2, [r3, #16]
80003dc: 4b24 ldr r3, [pc, #144] ; (8000470 <TIM16_IRQHandler+0xa8>)
80003de: 2101 movs r1, #1
80003e0: 438a bics r2, r1
80003e2: 611a str r2, [r3, #16]
uint8_t bits = 0, mask = 1;
80003e4: 1dfb adds r3, r7, #7
80003e6: 2200 movs r2, #0
80003e8: 701a strb r2, [r3, #0]
80003ea: 1dbb adds r3, r7, #6
80003ec: 2201 movs r2, #1
80003ee: 701a strb r2, [r3, #0]
for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) {
80003f0: 2300 movs r3, #0
80003f2: 603b str r3, [r7, #0]
80003f4: e01d b.n 8000432 <TIM16_IRQHandler+0x6a>
if (leds.arr[i]) {
80003f6: 4b1f ldr r3, [pc, #124] ; (8000474 <TIM16_IRQHandler+0xac>)
80003f8: 683a ldr r2, [r7, #0]
80003fa: 0092 lsls r2, r2, #2
80003fc: 58d3 ldr r3, [r2, r3]
80003fe: 2b00 cmp r3, #0
8000400: d00f beq.n 8000422 <TIM16_IRQHandler+0x5a>
leds.arr[i]--;
8000402: 4b1c ldr r3, [pc, #112] ; (8000474 <TIM16_IRQHandler+0xac>)
8000404: 683a ldr r2, [r7, #0]
8000406: 0092 lsls r2, r2, #2
8000408: 58d3 ldr r3, [r2, r3]
800040a: 1e59 subs r1, r3, #1
800040c: 4b19 ldr r3, [pc, #100] ; (8000474 <TIM16_IRQHandler+0xac>)
800040e: 683a ldr r2, [r7, #0]
8000410: 0092 lsls r2, r2, #2
8000412: 50d1 str r1, [r2, r3]
bits |= mask;
8000414: 1dfb adds r3, r7, #7
8000416: 1df9 adds r1, r7, #7
8000418: 1dba adds r2, r7, #6
800041a: 7809 ldrb r1, [r1, #0]
800041c: 7812 ldrb r2, [r2, #0]
800041e: 430a orrs r2, r1
8000420: 701a strb r2, [r3, #0]
}
mask <<= 1;
8000422: 1dba adds r2, r7, #6
8000424: 1dbb adds r3, r7, #6
8000426: 781b ldrb r3, [r3, #0]
8000428: 18db adds r3, r3, r3
800042a: 7013 strb r3, [r2, #0]
for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) {
800042c: 683b ldr r3, [r7, #0]
800042e: 3301 adds r3, #1
8000430: 603b str r3, [r7, #0]
8000432: 683b ldr r3, [r7, #0]
8000434: 2b07 cmp r3, #7
8000436: d9de bls.n 80003f6 <TIM16_IRQHandler+0x2e>
}
if (leds_update_counter++ == 10) {
8000438: 4b0f ldr r3, [pc, #60] ; (8000478 <TIM16_IRQHandler+0xb0>)
800043a: 681b ldr r3, [r3, #0]
800043c: 1c59 adds r1, r3, #1
800043e: 4a0e ldr r2, [pc, #56] ; (8000478 <TIM16_IRQHandler+0xb0>)
8000440: 6011 str r1, [r2, #0]
8000442: 2b0a cmp r3, #10
8000444: d110 bne.n 8000468 <TIM16_IRQHandler+0xa0>
leds_update_counter = 0;
8000446: 4b0c ldr r3, [pc, #48] ; (8000478 <TIM16_IRQHandler+0xb0>)
8000448: 2200 movs r2, #0
800044a: 601a str r2, [r3, #0]
/* Workaround for SPI hardware bug: Even if configured to 8-bit mode, the SPI will do a 16-bit transfer if the
* data register is accessed through a 16-bit write. Unfortunately, the STMCube register defs define DR as an
* uint16_t, so we have to do some magic here to force an 8-bit write. */
*((volatile uint8_t*)&(SPI1->DR)) = bits;
800044c: 4a0b ldr r2, [pc, #44] ; (800047c <TIM16_IRQHandler+0xb4>)
800044e: 1dfb adds r3, r7, #7
8000450: 781b ldrb r3, [r3, #0]
8000452: 7013 strb r3, [r2, #0]
SPI1->CR2 |= SPI_CR2_TXEIE;
8000454: 4b0a ldr r3, [pc, #40] ; (8000480 <TIM16_IRQHandler+0xb8>)
8000456: 685a ldr r2, [r3, #4]
8000458: 4b09 ldr r3, [pc, #36] ; (8000480 <TIM16_IRQHandler+0xb8>)
800045a: 2180 movs r1, #128 ; 0x80
800045c: 430a orrs r2, r1
800045e: 605a str r2, [r3, #4]
GPIOA->BRR = 1<<3;
8000460: 2390 movs r3, #144 ; 0x90
8000462: 05db lsls r3, r3, #23
8000464: 2208 movs r2, #8
8000466: 629a str r2, [r3, #40] ; 0x28
}
}
}
8000468: 46c0 nop ; (mov r8, r8)
800046a: 46bd mov sp, r7
800046c: b002 add sp, #8
800046e: bd80 pop {r7, pc}
8000470: 40014400 .word 0x40014400
8000474: 20000178 .word 0x20000178
8000478: 20000098 .word 0x20000098
800047c: 4001300c .word 0x4001300c
8000480: 40013000 .word 0x40013000
08000484 <NMI_Handler>:
void NMI_Handler(void) {
8000484: b580 push {r7, lr}
8000486: af00 add r7, sp, #0
asm volatile ("bkpt");
8000488: be00 bkpt 0x0000
}
800048a: 46c0 nop ; (mov r8, r8)
800048c: 46bd mov sp, r7
800048e: bd80 pop {r7, pc}
08000490 <HardFault_Handler>:
void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler() {
asm volatile ("bkpt");
8000490: be00 bkpt 0x0000
}
8000492: 46c0 nop ; (mov r8, r8)
08000494 <SVC_Handler>:
void SVC_Handler(void) {
8000494: b580 push {r7, lr}
8000496: af00 add r7, sp, #0
asm volatile ("bkpt");
8000498: be00 bkpt 0x0000
}
800049a: 46c0 nop ; (mov r8, r8)
800049c: 46bd mov sp, r7
800049e: bd80 pop {r7, pc}
080004a0 <PendSV_Handler>:
void PendSV_Handler(void) {
80004a0: b580 push {r7, lr}
80004a2: af00 add r7, sp, #0
asm volatile ("bkpt");
80004a4: be00 bkpt 0x0000
}
80004a6: 46c0 nop ; (mov r8, r8)
80004a8: 46bd mov sp, r7
80004aa: bd80 pop {r7, pc}
080004ac <SysTick_Handler>:
void SysTick_Handler(void) {
80004ac: b580 push {r7, lr}
80004ae: af00 add r7, sp, #0
static int n = 0;
if (n++ == 10) {
80004b0: 4b0a ldr r3, [pc, #40] ; (80004dc <SysTick_Handler+0x30>)
80004b2: 681b ldr r3, [r3, #0]
80004b4: 1c59 adds r1, r3, #1
80004b6: 4a09 ldr r2, [pc, #36] ; (80004dc <SysTick_Handler+0x30>)
80004b8: 6011 str r1, [r2, #0]
80004ba: 2b0a cmp r3, #10
80004bc: d10a bne.n 80004d4 <SysTick_Handler+0x28>
n = 0;
80004be: 4b07 ldr r3, [pc, #28] ; (80004dc <SysTick_Handler+0x30>)
80004c0: 2200 movs r2, #0
80004c2: 601a str r2, [r3, #0]
sys_time_seconds++;
80004c4: 4b06 ldr r3, [pc, #24] ; (80004e0 <SysTick_Handler+0x34>)
80004c6: 681b ldr r3, [r3, #0]
80004c8: 1c5a adds r2, r3, #1
80004ca: 4b05 ldr r3, [pc, #20] ; (80004e0 <SysTick_Handler+0x34>)
80004cc: 601a str r2, [r3, #0]
leds.pps = 100; /* ms */
80004ce: 4b05 ldr r3, [pc, #20] ; (80004e4 <SysTick_Handler+0x38>)
80004d0: 2264 movs r2, #100 ; 0x64
80004d2: 619a str r2, [r3, #24]
}
}
80004d4: 46c0 nop ; (mov r8, r8)
80004d6: 46bd mov sp, r7
80004d8: bd80 pop {r7, pc}
80004da: 46c0 nop ; (mov r8, r8)
80004dc: 2000009c .word 0x2000009c
80004e0: 20000094 .word 0x20000094
80004e4: 20000178 .word 0x20000178
080004e8 <NVIC_EnableIRQ>:
{
80004e8: b580 push {r7, lr}
80004ea: b082 sub sp, #8
80004ec: af00 add r7, sp, #0
80004ee: 0002 movs r2, r0
80004f0: 1dfb adds r3, r7, #7
80004f2: 701a strb r2, [r3, #0]
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
80004f4: 1dfb adds r3, r7, #7
80004f6: 781b ldrb r3, [r3, #0]
80004f8: 001a movs r2, r3
80004fa: 231f movs r3, #31
80004fc: 401a ands r2, r3
80004fe: 4b04 ldr r3, [pc, #16] ; (8000510 <NVIC_EnableIRQ+0x28>)
8000500: 2101 movs r1, #1
8000502: 4091 lsls r1, r2
8000504: 000a movs r2, r1
8000506: 601a str r2, [r3, #0]
}
8000508: 46c0 nop ; (mov r8, r8)
800050a: 46bd mov sp, r7
800050c: b002 add sp, #8
800050e: bd80 pop {r7, pc}
8000510: e000e100 .word 0xe000e100
08000514 <NVIC_SetPriority>:
{
8000514: b590 push {r4, r7, lr}
8000516: b083 sub sp, #12
8000518: af00 add r7, sp, #0
800051a: 0002 movs r2, r0
800051c: 6039 str r1, [r7, #0]
800051e: 1dfb adds r3, r7, #7
8000520: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) < 0)
8000522: 1dfb adds r3, r7, #7
8000524: 781b ldrb r3, [r3, #0]
8000526: 2b7f cmp r3, #127 ; 0x7f
8000528: d932 bls.n 8000590 <NVIC_SetPriority+0x7c>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800052a: 4a2f ldr r2, [pc, #188] ; (80005e8 <NVIC_SetPriority+0xd4>)
800052c: 1dfb adds r3, r7, #7
800052e: 781b ldrb r3, [r3, #0]
8000530: 0019 movs r1, r3
8000532: 230f movs r3, #15
8000534: 400b ands r3, r1
8000536: 3b08 subs r3, #8
8000538: 089b lsrs r3, r3, #2
800053a: 3306 adds r3, #6
800053c: 009b lsls r3, r3, #2
800053e: 18d3 adds r3, r2, r3
8000540: 3304 adds r3, #4
8000542: 681b ldr r3, [r3, #0]
8000544: 1dfa adds r2, r7, #7
8000546: 7812 ldrb r2, [r2, #0]
8000548: 0011 movs r1, r2
800054a: 2203 movs r2, #3
800054c: 400a ands r2, r1
800054e: 00d2 lsls r2, r2, #3
8000550: 21ff movs r1, #255 ; 0xff
8000552: 4091 lsls r1, r2
8000554: 000a movs r2, r1
8000556: 43d2 mvns r2, r2
8000558: 401a ands r2, r3
800055a: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800055c: 683b ldr r3, [r7, #0]
800055e: 019b lsls r3, r3, #6
8000560: 22ff movs r2, #255 ; 0xff
8000562: 401a ands r2, r3
8000564: 1dfb adds r3, r7, #7
8000566: 781b ldrb r3, [r3, #0]
8000568: 0018 movs r0, r3
800056a: 2303 movs r3, #3
800056c: 4003 ands r3, r0
800056e: 00db lsls r3, r3, #3
8000570: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000572: 481d ldr r0, [pc, #116] ; (80005e8 <NVIC_SetPriority+0xd4>)
8000574: 1dfb adds r3, r7, #7
8000576: 781b ldrb r3, [r3, #0]
8000578: 001c movs r4, r3
800057a: 230f movs r3, #15
800057c: 4023 ands r3, r4
800057e: 3b08 subs r3, #8
8000580: 089b lsrs r3, r3, #2
8000582: 430a orrs r2, r1
8000584: 3306 adds r3, #6
8000586: 009b lsls r3, r3, #2
8000588: 18c3 adds r3, r0, r3
800058a: 3304 adds r3, #4
800058c: 601a str r2, [r3, #0]
}
800058e: e027 b.n 80005e0 <NVIC_SetPriority+0xcc>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000590: 4a16 ldr r2, [pc, #88] ; (80005ec <NVIC_SetPriority+0xd8>)
8000592: 1dfb adds r3, r7, #7
8000594: 781b ldrb r3, [r3, #0]
8000596: b25b sxtb r3, r3
8000598: 089b lsrs r3, r3, #2
800059a: 33c0 adds r3, #192 ; 0xc0
800059c: 009b lsls r3, r3, #2
800059e: 589b ldr r3, [r3, r2]
80005a0: 1dfa adds r2, r7, #7
80005a2: 7812 ldrb r2, [r2, #0]
80005a4: 0011 movs r1, r2
80005a6: 2203 movs r2, #3
80005a8: 400a ands r2, r1
80005aa: 00d2 lsls r2, r2, #3
80005ac: 21ff movs r1, #255 ; 0xff
80005ae: 4091 lsls r1, r2
80005b0: 000a movs r2, r1
80005b2: 43d2 mvns r2, r2
80005b4: 401a ands r2, r3
80005b6: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80005b8: 683b ldr r3, [r7, #0]
80005ba: 019b lsls r3, r3, #6
80005bc: 22ff movs r2, #255 ; 0xff
80005be: 401a ands r2, r3
80005c0: 1dfb adds r3, r7, #7
80005c2: 781b ldrb r3, [r3, #0]
80005c4: 0018 movs r0, r3
80005c6: 2303 movs r3, #3
80005c8: 4003 ands r3, r0
80005ca: 00db lsls r3, r3, #3
80005cc: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80005ce: 4807 ldr r0, [pc, #28] ; (80005ec <NVIC_SetPriority+0xd8>)
80005d0: 1dfb adds r3, r7, #7
80005d2: 781b ldrb r3, [r3, #0]
80005d4: b25b sxtb r3, r3
80005d6: 089b lsrs r3, r3, #2
80005d8: 430a orrs r2, r1
80005da: 33c0 adds r3, #192 ; 0xc0
80005dc: 009b lsls r3, r3, #2
80005de: 501a str r2, [r3, r0]
}
80005e0: 46c0 nop ; (mov r8, r8)
80005e2: 46bd mov sp, r7
80005e4: b003 add sp, #12
80005e6: bd90 pop {r4, r7, pc}
80005e8: e000ed00 .word 0xe000ed00
80005ec: e000e100 .word 0xe000e100
080005f0 <adc_configure_scope_mode>:
static void adc_timer_init(int psc, int ivl);
static void adc_dma_launch(void);
/* Mode that can be used for debugging */
void adc_configure_scope_mode(int sampling_interval_ns) {
80005f0: b580 push {r7, lr}
80005f2: b084 sub sp, #16
80005f4: af00 add r7, sp, #0
80005f6: 6078 str r0, [r7, #4]
adc_dma_init();
80005f8: f000 f84a bl 8000690 <adc_dma_init>
/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
80005fc: 4b20 ldr r3, [pc, #128] ; (8000680 <adc_configure_scope_mode+0x90>)
80005fe: 2280 movs r2, #128 ; 0x80
8000600: 0612 lsls r2, r2, #24
8000602: 611a str r2, [r3, #16]
/* Sampling time 239.5 ADC clock cycles -> total conversion time 38.5us*/
ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos);
8000604: 4b1e ldr r3, [pc, #120] ; (8000680 <adc_configure_scope_mode+0x90>)
8000606: 2207 movs r2, #7
8000608: 615a str r2, [r3, #20]
/* Setup DMA and triggering */
/* Trigger from TIM1 TRGO */
ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos);
800060a: 4b1d ldr r3, [pc, #116] ; (8000680 <adc_configure_scope_mode+0x90>)
800060c: 4a1d ldr r2, [pc, #116] ; (8000684 <adc_configure_scope_mode+0x94>)
800060e: 60da str r2, [r3, #12]
ADC1->CHSELR = ADC_CHSELR_CHSEL2;
8000610: 4b1b ldr r3, [pc, #108] ; (8000680 <adc_configure_scope_mode+0x90>)
8000612: 2204 movs r2, #4
8000614: 629a str r2, [r3, #40] ; 0x28
/* Perform self-calibration */
ADC1->CR |= ADC_CR_ADCAL;
8000616: 4b1a ldr r3, [pc, #104] ; (8000680 <adc_configure_scope_mode+0x90>)
8000618: 689a ldr r2, [r3, #8]
800061a: 4b19 ldr r3, [pc, #100] ; (8000680 <adc_configure_scope_mode+0x90>)
800061c: 2180 movs r1, #128 ; 0x80
800061e: 0609 lsls r1, r1, #24
8000620: 430a orrs r2, r1
8000622: 609a str r2, [r3, #8]
while (ADC1->CR & ADC_CR_ADCAL)
8000624: 46c0 nop ; (mov r8, r8)
8000626: 4b16 ldr r3, [pc, #88] ; (8000680 <adc_configure_scope_mode+0x90>)
8000628: 689b ldr r3, [r3, #8]
800062a: 2b00 cmp r3, #0
800062c: dbfb blt.n 8000626 <adc_configure_scope_mode+0x36>
;
/* Enable conversion */
ADC1->CR |= ADC_CR_ADEN;
800062e: 4b14 ldr r3, [pc, #80] ; (8000680 <adc_configure_scope_mode+0x90>)
8000630: 689a ldr r2, [r3, #8]
8000632: 4b13 ldr r3, [pc, #76] ; (8000680 <adc_configure_scope_mode+0x90>)
8000634: 2101 movs r1, #1
8000636: 430a orrs r2, r1
8000638: 609a str r2, [r3, #8]
ADC1->CR |= ADC_CR_ADSTART;
800063a: 4b11 ldr r3, [pc, #68] ; (8000680 <adc_configure_scope_mode+0x90>)
800063c: 689a ldr r2, [r3, #8]
800063e: 4b10 ldr r3, [pc, #64] ; (8000680 <adc_configure_scope_mode+0x90>)
8000640: 2104 movs r1, #4
8000642: 430a orrs r2, r1
8000644: 609a str r2, [r3, #8]
/* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us.
Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this
would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */
int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6;
8000646: 687b ldr r3, [r7, #4]
8000648: 4a0f ldr r2, [pc, #60] ; (8000688 <adc_configure_scope_mode+0x98>)
800064a: 4293 cmp r3, r2
800064c: dd06 ble.n 800065c <adc_configure_scope_mode+0x6c>
800064e: 687b ldr r3, [r7, #4]
8000650: 21fa movs r1, #250 ; 0xfa
8000652: 0018 movs r0, r3
8000654: f001 f9e6 bl 8001a24 <__divsi3>
8000658: 0003 movs r3, r0
800065a: e000 b.n 800065e <adc_configure_scope_mode+0x6e>
800065c: 2306 movs r3, #6
800065e: 60fb str r3, [r7, #12]
if (cycles > 0xffff)
8000660: 68fa ldr r2, [r7, #12]
8000662: 2380 movs r3, #128 ; 0x80
8000664: 025b lsls r3, r3, #9
8000666: 429a cmp r2, r3
8000668: db01 blt.n 800066e <adc_configure_scope_mode+0x7e>
cycles = 0xffff;
800066a: 4b08 ldr r3, [pc, #32] ; (800068c <adc_configure_scope_mode+0x9c>)
800066c: 60fb str r3, [r7, #12]
adc_timer_init(12/*250ns/tick*/, cycles);
800066e: 68fb ldr r3, [r7, #12]
8000670: 0019 movs r1, r3
8000672: 200c movs r0, #12
8000674: f000 f85a bl 800072c <adc_timer_init>
}
8000678: 46c0 nop ; (mov r8, r8)
800067a: 46bd mov sp, r7
800067c: b004 add sp, #16
800067e: bd80 pop {r7, pc}
8000680: 40012400 .word 0x40012400
8000684: 00000843 .word 0x00000843
8000688: 000005dc .word 0x000005dc
800068c: 0000ffff .word 0x0000ffff
08000690 <adc_dma_init>:
static void adc_dma_init() {
8000690: b580 push {r7, lr}
8000692: af00 add r7, sp, #0
/* Configure DMA 1 Channel 1 to get rid of all the data */
DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
8000694: 4b0b ldr r3, [pc, #44] ; (80006c4 <adc_dma_init+0x34>)
8000696: 4a0c ldr r2, [pc, #48] ; (80006c8 <adc_dma_init+0x38>)
8000698: 609a str r2, [r3, #8]
DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
800069a: 4b0a ldr r3, [pc, #40] ; (80006c4 <adc_dma_init+0x34>)
800069c: 2200 movs r2, #0
800069e: 601a str r2, [r3, #0]
DMA1_Channel1->CCR |=
80006a0: 4b08 ldr r3, [pc, #32] ; (80006c4 <adc_dma_init+0x34>)
80006a2: 681a ldr r2, [r3, #0]
80006a4: 4b07 ldr r3, [pc, #28] ; (80006c4 <adc_dma_init+0x34>)
80006a6: 4909 ldr r1, [pc, #36] ; (80006cc <adc_dma_init+0x3c>)
80006a8: 430a orrs r2, r1
80006aa: 601a str r2, [r3, #0]
| (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
| DMA_CCR_MINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
/* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
80006ac: 2009 movs r0, #9
80006ae: f7ff ff1b bl 80004e8 <NVIC_EnableIRQ>
NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5);
80006b2: 2140 movs r1, #64 ; 0x40
80006b4: 2009 movs r0, #9
80006b6: f7ff ff2d bl 8000514 <NVIC_SetPriority>
adc_dma_launch();
80006ba: f000 f809 bl 80006d0 <adc_dma_launch>
}
80006be: 46c0 nop ; (mov r8, r8)
80006c0: 46bd mov sp, r7
80006c2: bd80 pop {r7, pc}
80006c4: 40020008 .word 0x40020008
80006c8: 40012440 .word 0x40012440
80006cc: 00000582 .word 0x00000582
080006d0 <adc_dma_launch>:
void adc_dma_launch() {
80006d0: b580 push {r7, lr}
80006d2: af00 add r7, sp, #0
DMA1_Channel1->CCR &= ~DMA_CCR_EN; /* Disable channel */
80006d4: 4b12 ldr r3, [pc, #72] ; (8000720 <adc_dma_launch+0x50>)
80006d6: 681a ldr r2, [r3, #0]
80006d8: 4b11 ldr r3, [pc, #68] ; (8000720 <adc_dma_launch+0x50>)
80006da: 2101 movs r1, #1
80006dc: 438a bics r2, r1
80006de: 601a str r2, [r3, #0]
current_buf = !current_buf;
80006e0: 4b10 ldr r3, [pc, #64] ; (8000724 <adc_dma_launch+0x54>)
80006e2: 681b ldr r3, [r3, #0]
80006e4: 425a negs r2, r3
80006e6: 4153 adcs r3, r2
80006e8: b2db uxtb r3, r3
80006ea: 001a movs r2, r3
80006ec: 4b0d ldr r3, [pc, #52] ; (8000724 <adc_dma_launch+0x54>)
80006ee: 601a str r2, [r3, #0]
DMA1_Channel1->CMAR = (unsigned int)&(adc_pkt[current_buf].data);
80006f0: 4b0c ldr r3, [pc, #48] ; (8000724 <adc_dma_launch+0x54>)
80006f2: 681a ldr r2, [r3, #0]
80006f4: 0013 movs r3, r2
80006f6: 00db lsls r3, r3, #3
80006f8: 189b adds r3, r3, r2
80006fa: 00db lsls r3, r3, #3
80006fc: 3308 adds r3, #8
80006fe: 001a movs r2, r3
8000700: 4b09 ldr r3, [pc, #36] ; (8000728 <adc_dma_launch+0x58>)
8000702: 18d2 adds r2, r2, r3
8000704: 4b06 ldr r3, [pc, #24] ; (8000720 <adc_dma_launch+0x50>)
8000706: 60da str r2, [r3, #12]
DMA1_Channel1->CNDTR = ARRAY_LEN(adc_pkt[current_buf].data);
8000708: 4b05 ldr r3, [pc, #20] ; (8000720 <adc_dma_launch+0x50>)
800070a: 2220 movs r2, #32
800070c: 605a str r2, [r3, #4]
DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
800070e: 4b04 ldr r3, [pc, #16] ; (8000720 <adc_dma_launch+0x50>)
8000710: 681a ldr r2, [r3, #0]
8000712: 4b03 ldr r3, [pc, #12] ; (8000720 <adc_dma_launch+0x50>)
8000714: 2101 movs r1, #1
8000716: 430a orrs r2, r1
8000718: 601a str r2, [r3, #0]
}
800071a: 46c0 nop ; (mov r8, r8)
800071c: 46bd mov sp, r7
800071e: bd80 pop {r7, pc}
8000720: 40020008 .word 0x40020008
8000724: 20000134 .word 0x20000134
8000728: 200000a0 .word 0x200000a0
0800072c <adc_timer_init>:
static void adc_timer_init(int psc, int ivl) {
800072c: b580 push {r7, lr}
800072e: b082 sub sp, #8
8000730: af00 add r7, sp, #0
8000732: 6078 str r0, [r7, #4]
8000734: 6039 str r1, [r7, #0]
TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */
8000736: 4b15 ldr r3, [pc, #84] ; (800078c <adc_timer_init+0x60>)
8000738: 2280 movs r2, #128 ; 0x80
800073a: 0212 lsls r2, r2, #8
800073c: 645a str r2, [r3, #68] ; 0x44
TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
800073e: 4b13 ldr r3, [pc, #76] ; (800078c <adc_timer_init+0x60>)
8000740: 22c0 movs r2, #192 ; 0xc0
8000742: 01d2 lsls r2, r2, #7
8000744: 61da str r2, [r3, #28]
TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
8000746: 4b11 ldr r3, [pc, #68] ; (800078c <adc_timer_init+0x60>)
8000748: 2280 movs r2, #128 ; 0x80
800074a: 0152 lsls r2, r2, #5
800074c: 621a str r2, [r3, #32]
TIM1->CCR4 = 1; /* Trigger at start of timer cycle */
800074e: 4b0f ldr r3, [pc, #60] ; (800078c <adc_timer_init+0x60>)
8000750: 2201 movs r2, #1
8000752: 641a str r2, [r3, #64] ; 0x40
/* Set prescaler and interval */
TIM1->PSC = psc-1;
8000754: 687b ldr r3, [r7, #4]
8000756: 1e5a subs r2, r3, #1
8000758: 4b0c ldr r3, [pc, #48] ; (800078c <adc_timer_init+0x60>)
800075a: 629a str r2, [r3, #40] ; 0x28
TIM1->ARR = ivl-1;
800075c: 683b ldr r3, [r7, #0]
800075e: 1e5a subs r2, r3, #1
8000760: 4b0a ldr r3, [pc, #40] ; (800078c <adc_timer_init+0x60>)
8000762: 62da str r2, [r3, #44] ; 0x2c
/* Preload all values */
TIM1->EGR |= TIM_EGR_UG;
8000764: 4b09 ldr r3, [pc, #36] ; (800078c <adc_timer_init+0x60>)
8000766: 695a ldr r2, [r3, #20]
8000768: 4b08 ldr r3, [pc, #32] ; (800078c <adc_timer_init+0x60>)
800076a: 2101 movs r1, #1
800076c: 430a orrs r2, r1
800076e: 615a str r2, [r3, #20]
TIM1->CR1 = TIM_CR1_ARPE;
8000770: 4b06 ldr r3, [pc, #24] ; (800078c <adc_timer_init+0x60>)
8000772: 2280 movs r2, #128 ; 0x80
8000774: 601a str r2, [r3, #0]
/* And... go! */
TIM1->CR1 |= TIM_CR1_CEN;
8000776: 4b05 ldr r3, [pc, #20] ; (800078c <adc_timer_init+0x60>)
8000778: 681a ldr r2, [r3, #0]
800077a: 4b04 ldr r3, [pc, #16] ; (800078c <adc_timer_init+0x60>)
800077c: 2101 movs r1, #1
800077e: 430a orrs r2, r1
8000780: 601a str r2, [r3, #0]
}
8000782: 46c0 nop ; (mov r8, r8)
8000784: 46bd mov sp, r7
8000786: b002 add sp, #8
8000788: bd80 pop {r7, pc}
800078a: 46c0 nop ; (mov r8, r8)
800078c: 40012c00 .word 0x40012c00
08000790 <gdb_dump>:
/* This acts as a no-op that provides a convenient point to set a breakpoint for the debug scope logic */
static void gdb_dump(void) {
8000790: b580 push {r7, lr}
8000792: af00 add r7, sp, #0
}
8000794: 46c0 nop ; (mov r8, r8)
8000796: 46bd mov sp, r7
8000798: bd80 pop {r7, pc}
0800079a <DMA1_Channel1_IRQHandler>:
void DMA1_Channel1_IRQHandler(void) {
800079a: b580 push {r7, lr}
800079c: b082 sub sp, #8
800079e: af00 add r7, sp, #0
uint32_t isr = DMA1->ISR;
80007a0: 4b1a ldr r3, [pc, #104] ; (800080c <DMA1_Channel1_IRQHandler+0x72>)
80007a2: 681b ldr r3, [r3, #0]
80007a4: 607b str r3, [r7, #4]
/* Clear the interrupt flag */
DMA1->IFCR |= DMA_IFCR_CGIF1;
80007a6: 4b19 ldr r3, [pc, #100] ; (800080c <DMA1_Channel1_IRQHandler+0x72>)
80007a8: 685a ldr r2, [r3, #4]
80007aa: 4b18 ldr r3, [pc, #96] ; (800080c <DMA1_Channel1_IRQHandler+0x72>)
80007ac: 2101 movs r1, #1
80007ae: 430a orrs r2, r1
80007b0: 605a str r2, [r3, #4]
adc_dma_launch();
80007b2: f7ff ff8d bl 80006d0 <adc_dma_launch>
gdb_dump();
80007b6: f7ff ffeb bl 8000790 <gdb_dump>
adc_pkt[!current_buf].seq = current_seq++;
80007ba: 4b15 ldr r3, [pc, #84] ; (8000810 <DMA1_Channel1_IRQHandler+0x76>)
80007bc: 881a ldrh r2, [r3, #0]
80007be: 1c53 adds r3, r2, #1
80007c0: b299 uxth r1, r3
80007c2: 4b13 ldr r3, [pc, #76] ; (8000810 <DMA1_Channel1_IRQHandler+0x76>)
80007c4: 8019 strh r1, [r3, #0]
80007c6: 4b13 ldr r3, [pc, #76] ; (8000814 <DMA1_Channel1_IRQHandler+0x7a>)
80007c8: 681b ldr r3, [r3, #0]
80007ca: 4259 negs r1, r3
80007cc: 414b adcs r3, r1
80007ce: b2db uxtb r3, r3
80007d0: 0018 movs r0, r3
80007d2: 4911 ldr r1, [pc, #68] ; (8000818 <DMA1_Channel1_IRQHandler+0x7e>)
80007d4: 0003 movs r3, r0
80007d6: 00db lsls r3, r3, #3
80007d8: 181b adds r3, r3, r0
80007da: 00db lsls r3, r3, #3
80007dc: 18cb adds r3, r1, r3
80007de: 3306 adds r3, #6
80007e0: 801a strh r2, [r3, #0]
/* Ignore return value since we can't do anything here. Overruns are logged in serial.c. */
usart_send_packet_nonblocking(&adc_pkt[!current_buf].ll, sizeof(adc_pkt[!current_buf]));
80007e2: 4b0c ldr r3, [pc, #48] ; (8000814 <DMA1_Channel1_IRQHandler+0x7a>)
80007e4: 681b ldr r3, [r3, #0]
80007e6: 425a negs r2, r3
80007e8: 4153 adcs r3, r2
80007ea: b2db uxtb r3, r3
80007ec: 001a movs r2, r3
80007ee: 0013 movs r3, r2
80007f0: 00db lsls r3, r3, #3
80007f2: 189b adds r3, r3, r2
80007f4: 00db lsls r3, r3, #3
80007f6: 4a08 ldr r2, [pc, #32] ; (8000818 <DMA1_Channel1_IRQHandler+0x7e>)
80007f8: 189b adds r3, r3, r2
80007fa: 2148 movs r1, #72 ; 0x48
80007fc: 0018 movs r0, r3
80007fe: f000 fadd bl 8000dbc <usart_send_packet_nonblocking>
adc_buf[i] = -255;
}
}
}
*/
}
8000802: 46c0 nop ; (mov r8, r8)
8000804: 46bd mov sp, r7
8000806: b002 add sp, #8
8000808: bd80 pop {r7, pc}
800080a: 46c0 nop ; (mov r8, r8)
800080c: 40020000 .word 0x40020000
8000810: 20000130 .word 0x20000130
8000814: 20000134 .word 0x20000134
8000818: 200000a0 .word 0x200000a0
0800081c <NVIC_EnableIRQ>:
{
800081c: b580 push {r7, lr}
800081e: b082 sub sp, #8
8000820: af00 add r7, sp, #0
8000822: 0002 movs r2, r0
8000824: 1dfb adds r3, r7, #7
8000826: 701a strb r2, [r3, #0]
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
8000828: 1dfb adds r3, r7, #7
800082a: 781b ldrb r3, [r3, #0]
800082c: 001a movs r2, r3
800082e: 231f movs r3, #31
8000830: 401a ands r2, r3
8000832: 4b04 ldr r3, [pc, #16] ; (8000844 <NVIC_EnableIRQ+0x28>)
8000834: 2101 movs r1, #1
8000836: 4091 lsls r1, r2
8000838: 000a movs r2, r1
800083a: 601a str r2, [r3, #0]
}
800083c: 46c0 nop ; (mov r8, r8)
800083e: 46bd mov sp, r7
8000840: b002 add sp, #8
8000842: bd80 pop {r7, pc}
8000844: e000e100 .word 0xe000e100
08000848 <NVIC_DisableIRQ>:
{
8000848: b580 push {r7, lr}
800084a: b082 sub sp, #8
800084c: af00 add r7, sp, #0
800084e: 0002 movs r2, r0
8000850: 1dfb adds r3, r7, #7
8000852: 701a strb r2, [r3, #0]
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
8000854: 1dfb adds r3, r7, #7
8000856: 781b ldrb r3, [r3, #0]
8000858: 001a movs r2, r3
800085a: 231f movs r3, #31
800085c: 4013 ands r3, r2
800085e: 4905 ldr r1, [pc, #20] ; (8000874 <NVIC_DisableIRQ+0x2c>)
8000860: 2201 movs r2, #1
8000862: 409a lsls r2, r3
8000864: 0013 movs r3, r2
8000866: 2280 movs r2, #128 ; 0x80
8000868: 508b str r3, [r1, r2]
}
800086a: 46c0 nop ; (mov r8, r8)
800086c: 46bd mov sp, r7
800086e: b002 add sp, #8
8000870: bd80 pop {r7, pc}
8000872: 46c0 nop ; (mov r8, r8)
8000874: e000e100 .word 0xe000e100
08000878 <NVIC_SetPriority>:
{
8000878: b590 push {r4, r7, lr}
800087a: b083 sub sp, #12
800087c: af00 add r7, sp, #0
800087e: 0002 movs r2, r0
8000880: 6039 str r1, [r7, #0]
8000882: 1dfb adds r3, r7, #7
8000884: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) < 0)
8000886: 1dfb adds r3, r7, #7
8000888: 781b ldrb r3, [r3, #0]
800088a: 2b7f cmp r3, #127 ; 0x7f
800088c: d932 bls.n 80008f4 <NVIC_SetPriority+0x7c>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
800088e: 4a2f ldr r2, [pc, #188] ; (800094c <NVIC_SetPriority+0xd4>)
8000890: 1dfb adds r3, r7, #7
8000892: 781b ldrb r3, [r3, #0]
8000894: 0019 movs r1, r3
8000896: 230f movs r3, #15
8000898: 400b ands r3, r1
800089a: 3b08 subs r3, #8
800089c: 089b lsrs r3, r3, #2
800089e: 3306 adds r3, #6
80008a0: 009b lsls r3, r3, #2
80008a2: 18d3 adds r3, r2, r3
80008a4: 3304 adds r3, #4
80008a6: 681b ldr r3, [r3, #0]
80008a8: 1dfa adds r2, r7, #7
80008aa: 7812 ldrb r2, [r2, #0]
80008ac: 0011 movs r1, r2
80008ae: 2203 movs r2, #3
80008b0: 400a ands r2, r1
80008b2: 00d2 lsls r2, r2, #3
80008b4: 21ff movs r1, #255 ; 0xff
80008b6: 4091 lsls r1, r2
80008b8: 000a movs r2, r1
80008ba: 43d2 mvns r2, r2
80008bc: 401a ands r2, r3
80008be: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80008c0: 683b ldr r3, [r7, #0]
80008c2: 019b lsls r3, r3, #6
80008c4: 22ff movs r2, #255 ; 0xff
80008c6: 401a ands r2, r3
80008c8: 1dfb adds r3, r7, #7
80008ca: 781b ldrb r3, [r3, #0]
80008cc: 0018 movs r0, r3
80008ce: 2303 movs r3, #3
80008d0: 4003 ands r3, r0
80008d2: 00db lsls r3, r3, #3
80008d4: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80008d6: 481d ldr r0, [pc, #116] ; (800094c <NVIC_SetPriority+0xd4>)
80008d8: 1dfb adds r3, r7, #7
80008da: 781b ldrb r3, [r3, #0]
80008dc: 001c movs r4, r3
80008de: 230f movs r3, #15
80008e0: 4023 ands r3, r4
80008e2: 3b08 subs r3, #8
80008e4: 089b lsrs r3, r3, #2
80008e6: 430a orrs r2, r1
80008e8: 3306 adds r3, #6
80008ea: 009b lsls r3, r3, #2
80008ec: 18c3 adds r3, r0, r3
80008ee: 3304 adds r3, #4
80008f0: 601a str r2, [r3, #0]
}
80008f2: e027 b.n 8000944 <NVIC_SetPriority+0xcc>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80008f4: 4a16 ldr r2, [pc, #88] ; (8000950 <NVIC_SetPriority+0xd8>)
80008f6: 1dfb adds r3, r7, #7
80008f8: 781b ldrb r3, [r3, #0]
80008fa: b25b sxtb r3, r3
80008fc: 089b lsrs r3, r3, #2
80008fe: 33c0 adds r3, #192 ; 0xc0
8000900: 009b lsls r3, r3, #2
8000902: 589b ldr r3, [r3, r2]
8000904: 1dfa adds r2, r7, #7
8000906: 7812 ldrb r2, [r2, #0]
8000908: 0011 movs r1, r2
800090a: 2203 movs r2, #3
800090c: 400a ands r2, r1
800090e: 00d2 lsls r2, r2, #3
8000910: 21ff movs r1, #255 ; 0xff
8000912: 4091 lsls r1, r2
8000914: 000a movs r2, r1
8000916: 43d2 mvns r2, r2
8000918: 401a ands r2, r3
800091a: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800091c: 683b ldr r3, [r7, #0]
800091e: 019b lsls r3, r3, #6
8000920: 22ff movs r2, #255 ; 0xff
8000922: 401a ands r2, r3
8000924: 1dfb adds r3, r7, #7
8000926: 781b ldrb r3, [r3, #0]
8000928: 0018 movs r0, r3
800092a: 2303 movs r3, #3
800092c: 4003 ands r3, r0
800092e: 00db lsls r3, r3, #3
8000930: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8000932: 4807 ldr r0, [pc, #28] ; (8000950 <NVIC_SetPriority+0xd8>)
8000934: 1dfb adds r3, r7, #7
8000936: 781b ldrb r3, [r3, #0]
8000938: b25b sxtb r3, r3
800093a: 089b lsrs r3, r3, #2
800093c: 430a orrs r2, r1
800093e: 33c0 adds r3, #192 ; 0xc0
8000940: 009b lsls r3, r3, #2
8000942: 501a str r2, [r3, r0]
}
8000944: 46c0 nop ; (mov r8, r8)
8000946: 46bd mov sp, r7
8000948: b003 add sp, #12
800094a: bd90 pop {r4, r7, pc}
800094c: e000ed00 .word 0xe000ed00
8000950: e000e100 .word 0xe000e100
08000954 <usart_dma_init>:
static void usart_schedule_dma(void);
static int usart_putc_nonblocking(uint8_t c);
static int usart_retransmit_packet(uint8_t idx);
void usart_dma_init() {
8000954: b580 push {r7, lr}
8000956: b082 sub sp, #8
8000958: af00 add r7, sp, #0
usart_tx_buf.xfr_start = -1;
800095a: 4b2a ldr r3, [pc, #168] ; (8000a04 <usart_dma_init+0xb0>)
800095c: 2201 movs r2, #1
800095e: 4252 negs r2, r2
8000960: 601a str r2, [r3, #0]
usart_tx_buf.xfr_end = 0;
8000962: 4b28 ldr r3, [pc, #160] ; (8000a04 <usart_dma_init+0xb0>)
8000964: 2200 movs r2, #0
8000966: 605a str r2, [r3, #4]
usart_tx_buf.wr_pos = 0;
8000968: 4b26 ldr r3, [pc, #152] ; (8000a04 <usart_dma_init+0xb0>)
800096a: 2200 movs r2, #0
800096c: 609a str r2, [r3, #8]
for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
800096e: 2300 movs r3, #0
8000970: 607b str r3, [r7, #4]
8000972: e00b b.n 800098c <usart_dma_init+0x38>
usart_tx_buf.packet_start[i] = -1;
8000974: 4a23 ldr r2, [pc, #140] ; (8000a04 <usart_dma_init+0xb0>)
8000976: 687b ldr r3, [r7, #4]
8000978: 3302 adds r3, #2
800097a: 009b lsls r3, r3, #2
800097c: 18d3 adds r3, r2, r3
800097e: 3304 adds r3, #4
8000980: 2201 movs r2, #1
8000982: 4252 negs r2, r2
8000984: 601a str r2, [r3, #0]
for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
8000986: 687b ldr r3, [r7, #4]
8000988: 3301 adds r3, #1
800098a: 607b str r3, [r7, #4]
800098c: 687b ldr r3, [r7, #4]
800098e: 2b04 cmp r3, #4
8000990: d9f0 bls.n 8000974 <usart_dma_init+0x20>
cobs_decode_incremental_initialize(&cobs_state);
8000992: 4b1d ldr r3, [pc, #116] ; (8000a08 <usart_dma_init+0xb4>)
8000994: 0018 movs r0, r3
8000996: f000 fb6b bl 8001070 <cobs_decode_incremental_initialize>
/* Configure DMA 1 Channel 2 to handle uart transmission */
DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR);
800099a: 4b1c ldr r3, [pc, #112] ; (8000a0c <usart_dma_init+0xb8>)
800099c: 4a1c ldr r2, [pc, #112] ; (8000a10 <usart_dma_init+0xbc>)
800099e: 609a str r2, [r3, #8]
DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos)
80009a0: 4b1a ldr r3, [pc, #104] ; (8000a0c <usart_dma_init+0xb8>)
80009a2: 2292 movs r2, #146 ; 0x92
80009a4: 601a str r2, [r3, #0]
| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
| DMA_CCR_MINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
DMA1_Channel3->CMAR = (uint32_t)&(CRC->DR);
80009a6: 4b1b ldr r3, [pc, #108] ; (8000a14 <usart_dma_init+0xc0>)
80009a8: 4a1b ldr r2, [pc, #108] ; (8000a18 <usart_dma_init+0xc4>)
80009aa: 60da str r2, [r3, #12]
DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos)
80009ac: 4b19 ldr r3, [pc, #100] ; (8000a14 <usart_dma_init+0xc0>)
80009ae: 4a1b ldr r2, [pc, #108] ; (8000a1c <usart_dma_init+0xc8>)
80009b0: 601a str r2, [r3, #0]
| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
| DMA_CCR_PINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
/* triggered on transfer completion. We use this to process the ADC data */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
80009b2: 200a movs r0, #10
80009b4: f7ff ff32 bl 800081c <NVIC_EnableIRQ>
NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5);
80009b8: 2120 movs r1, #32
80009ba: 200a movs r0, #10
80009bc: f7ff ff5c bl 8000878 <NVIC_SetPriority>
USART1->CR1 = /* 8-bit -> M1, M0 clear */
80009c0: 4b17 ldr r3, [pc, #92] ; (8000a20 <usart_dma_init+0xcc>)
80009c2: 4a18 ldr r2, [pc, #96] ; (8000a24 <usart_dma_init+0xd0>)
80009c4: 601a str r2, [r3, #0]
/* Set divider for 115.2kBd @48MHz system clock. */
//USART1->BRR = 417;
//USART1->BRR = 48; /* 1MBd */
//USART1->BRR = 96; /* 500kBd */
USART1->BRR = 192; /* 250kBd */
80009c6: 4b16 ldr r3, [pc, #88] ; (8000a20 <usart_dma_init+0xcc>)
80009c8: 22c0 movs r2, #192 ; 0xc0
80009ca: 60da str r2, [r3, #12]
//USART1->BRR = 208; /* 230400 */
USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV;
80009cc: 4b14 ldr r3, [pc, #80] ; (8000a20 <usart_dma_init+0xcc>)
80009ce: 22c0 movs r2, #192 ; 0xc0
80009d0: 0292 lsls r2, r2, #10
80009d2: 605a str r2, [r3, #4]
USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */
80009d4: 4b12 ldr r3, [pc, #72] ; (8000a20 <usart_dma_init+0xcc>)
80009d6: 689a ldr r2, [r3, #8]
80009d8: 4b11 ldr r3, [pc, #68] ; (8000a20 <usart_dma_init+0xcc>)
80009da: 2180 movs r1, #128 ; 0x80
80009dc: 430a orrs r2, r1
80009de: 609a str r2, [r3, #8]
/* Enable receive interrupt */
NVIC_EnableIRQ(USART1_IRQn);
80009e0: 201b movs r0, #27
80009e2: f7ff ff1b bl 800081c <NVIC_EnableIRQ>
NVIC_SetPriority(USART1_IRQn, 3<<5);
80009e6: 2160 movs r1, #96 ; 0x60
80009e8: 201b movs r0, #27
80009ea: f7ff ff45 bl 8000878 <NVIC_SetPriority>
/* And... go! */
USART1->CR1 |= USART_CR1_UE;
80009ee: 4b0c ldr r3, [pc, #48] ; (8000a20 <usart_dma_init+0xcc>)
80009f0: 681a ldr r2, [r3, #0]
80009f2: 4b0b ldr r3, [pc, #44] ; (8000a20 <usart_dma_init+0xcc>)
80009f4: 2101 movs r1, #1
80009f6: 430a orrs r2, r1
80009f8: 601a str r2, [r3, #0]
}
80009fa: 46c0 nop ; (mov r8, r8)
80009fc: 46bd mov sp, r7
80009fe: b002 add sp, #8
8000a00: bd80 pop {r7, pc}
8000a02: 46c0 nop ; (mov r8, r8)
8000a04: 20000198 .word 0x20000198
8000a08: 20000148 .word 0x20000148
8000a0c: 4002001c .word 0x4002001c
8000a10: 40013828 .word 0x40013828
8000a14: 40020030 .word 0x40020030
8000a18: 40023000 .word 0x40023000
8000a1c: 00001042 .word 0x00001042
8000a20: 40013800 .word 0x40013800
8000a24: 0000202c .word 0x0000202c
08000a28 <USART1_IRQHandler>:
void USART1_IRQHandler() {
8000a28: b580 push {r7, lr}
8000a2a: b086 sub sp, #24
8000a2c: af00 add r7, sp, #0
uint32_t isr = USART1->ISR;
8000a2e: 4b41 ldr r3, [pc, #260] ; (8000b34 <USART1_IRQHandler+0x10c>)
8000a30: 69db ldr r3, [r3, #28]
8000a32: 613b str r3, [r7, #16]
if (isr & USART_ISR_ORE) {
8000a34: 693b ldr r3, [r7, #16]
8000a36: 2208 movs r2, #8
8000a38: 4013 ands r3, r2
8000a3a: d008 beq.n 8000a4e <USART1_IRQHandler+0x26>
USART1->ICR = USART_ICR_ORECF;
8000a3c: 4b3d ldr r3, [pc, #244] ; (8000b34 <USART1_IRQHandler+0x10c>)
8000a3e: 2208 movs r2, #8
8000a40: 621a str r2, [r3, #32]
rx_overruns++;
8000a42: 4b3d ldr r3, [pc, #244] ; (8000b38 <USART1_IRQHandler+0x110>)
8000a44: 681b ldr r3, [r3, #0]
8000a46: 1c5a adds r2, r3, #1
8000a48: 4b3b ldr r3, [pc, #236] ; (8000b38 <USART1_IRQHandler+0x110>)
8000a4a: 601a str r2, [r3, #0]
return;
8000a4c: e06f b.n 8000b2e <USART1_IRQHandler+0x106>
}
if (isr & USART_ISR_RXNE) {
8000a4e: 693b ldr r3, [r7, #16]
8000a50: 2220 movs r2, #32
8000a52: 4013 ands r3, r2
8000a54: d100 bne.n 8000a58 <USART1_IRQHandler+0x30>
8000a56: e06a b.n 8000b2e <USART1_IRQHandler+0x106>
uint8_t c = USART1->RDR;
8000a58: 4b36 ldr r3, [pc, #216] ; (8000b34 <USART1_IRQHandler+0x10c>)
8000a5a: 8c9b ldrh r3, [r3, #36] ; 0x24
8000a5c: b29a uxth r2, r3
8000a5e: 210f movs r1, #15
8000a60: 187b adds r3, r7, r1
8000a62: 701a strb r2, [r3, #0]
int rc = cobs_decode_incremental(&cobs_state, (char *)rx_buf, sizeof(rx_buf), c);
8000a64: 187b adds r3, r7, r1
8000a66: 781b ldrb r3, [r3, #0]
8000a68: 4934 ldr r1, [pc, #208] ; (8000b3c <USART1_IRQHandler+0x114>)
8000a6a: 4835 ldr r0, [pc, #212] ; (8000b40 <USART1_IRQHandler+0x118>)
8000a6c: 2220 movs r2, #32
8000a6e: f000 fb0d bl 800108c <cobs_decode_incremental>
8000a72: 0003 movs r3, r0
8000a74: 60bb str r3, [r7, #8]
if (rc == 0) /* packet still incomplete */
8000a76: 68bb ldr r3, [r7, #8]
8000a78: 2b00 cmp r3, #0
8000a7a: d057 beq.n 8000b2c <USART1_IRQHandler+0x104>
return;
if (rc < 0) {
8000a7c: 68bb ldr r3, [r7, #8]
8000a7e: 2b00 cmp r3, #0
8000a80: da05 bge.n 8000a8e <USART1_IRQHandler+0x66>
rx_framing_errors++;
8000a82: 4b30 ldr r3, [pc, #192] ; (8000b44 <USART1_IRQHandler+0x11c>)
8000a84: 681b ldr r3, [r3, #0]
8000a86: 1c5a adds r2, r3, #1
8000a88: 4b2e ldr r3, [pc, #184] ; (8000b44 <USART1_IRQHandler+0x11c>)
8000a8a: 601a str r2, [r3, #0]
return;
8000a8c: e04f b.n 8000b2e <USART1_IRQHandler+0x106>
}
/* A complete frame received */
if (rc != 2) {
8000a8e: 68bb ldr r3, [r7, #8]
8000a90: 2b02 cmp r3, #2
8000a92: d005 beq.n 8000aa0 <USART1_IRQHandler+0x78>
rx_protocol_errors++;
8000a94: 4b2c ldr r3, [pc, #176] ; (8000b48 <USART1_IRQHandler+0x120>)
8000a96: 681b ldr r3, [r3, #0]
8000a98: 1c5a adds r2, r3, #1
8000a9a: 4b2b ldr r3, [pc, #172] ; (8000b48 <USART1_IRQHandler+0x120>)
8000a9c: 601a str r2, [r3, #0]
return;
8000a9e: e046 b.n 8000b2e <USART1_IRQHandler+0x106>
}
volatile struct ctrl_pkt *pkt = (volatile struct ctrl_pkt *)rx_buf;
8000aa0: 4b26 ldr r3, [pc, #152] ; (8000b3c <USART1_IRQHandler+0x114>)
8000aa2: 607b str r3, [r7, #4]
switch (pkt->type) {
8000aa4: 687b ldr r3, [r7, #4]
8000aa6: 781b ldrb r3, [r3, #0]
8000aa8: b2db uxtb r3, r3
8000aaa: 2b03 cmp r3, #3
8000aac: d026 beq.n 8000afc <USART1_IRQHandler+0xd4>
8000aae: dc33 bgt.n 8000b18 <USART1_IRQHandler+0xf0>
8000ab0: 2b01 cmp r3, #1
8000ab2: d002 beq.n 8000aba <USART1_IRQHandler+0x92>
8000ab4: 2b02 cmp r3, #2
8000ab6: d013 beq.n 8000ae0 <USART1_IRQHandler+0xb8>
8000ab8: e02e b.n 8000b18 <USART1_IRQHandler+0xf0>
case CTRL_PKT_RESET:
for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
8000aba: 2300 movs r3, #0
8000abc: 617b str r3, [r7, #20]
8000abe: e00b b.n 8000ad8 <USART1_IRQHandler+0xb0>
usart_tx_buf.packet_start[i] = -1;
8000ac0: 4a22 ldr r2, [pc, #136] ; (8000b4c <USART1_IRQHandler+0x124>)
8000ac2: 697b ldr r3, [r7, #20]
8000ac4: 3302 adds r3, #2
8000ac6: 009b lsls r3, r3, #2
8000ac8: 18d3 adds r3, r2, r3
8000aca: 3304 adds r3, #4
8000acc: 2201 movs r2, #1
8000ace: 4252 negs r2, r2
8000ad0: 601a str r2, [r3, #0]
for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_start); i++)
8000ad2: 697b ldr r3, [r7, #20]
8000ad4: 3301 adds r3, #1
8000ad6: 617b str r3, [r7, #20]
8000ad8: 697b ldr r3, [r7, #20]
8000ada: 2b04 cmp r3, #4
8000adc: d9f0 bls.n 8000ac0 <USART1_IRQHandler+0x98>
break;
8000ade: e024 b.n 8000b2a <USART1_IRQHandler+0x102>
case CTRL_PKT_ACK:
if (usart_ack_packet(pkt->orig_id))
8000ae0: 687b ldr r3, [r7, #4]
8000ae2: 785b ldrb r3, [r3, #1]
8000ae4: b2db uxtb r3, r3
8000ae6: 0018 movs r0, r3
8000ae8: f000 f86c bl 8000bc4 <usart_ack_packet>
8000aec: 1e03 subs r3, r0, #0
8000aee: d019 beq.n 8000b24 <USART1_IRQHandler+0xfc>
rx_protocol_errors++;
8000af0: 4b15 ldr r3, [pc, #84] ; (8000b48 <USART1_IRQHandler+0x120>)
8000af2: 681b ldr r3, [r3, #0]
8000af4: 1c5a adds r2, r3, #1
8000af6: 4b14 ldr r3, [pc, #80] ; (8000b48 <USART1_IRQHandler+0x120>)
8000af8: 601a str r2, [r3, #0]
break;
8000afa: e013 b.n 8000b24 <USART1_IRQHandler+0xfc>
case CTRL_PKT_RETRANSMIT:
if (usart_retransmit_packet(pkt->orig_id))
8000afc: 687b ldr r3, [r7, #4]
8000afe: 785b ldrb r3, [r3, #1]
8000b00: b2db uxtb r3, r3
8000b02: 0018 movs r0, r3
8000b04: f000 f904 bl 8000d10 <usart_retransmit_packet>
8000b08: 1e03 subs r3, r0, #0
8000b0a: d00d beq.n 8000b28 <USART1_IRQHandler+0x100>
rx_protocol_errors++;
8000b0c: 4b0e ldr r3, [pc, #56] ; (8000b48 <USART1_IRQHandler+0x120>)
8000b0e: 681b ldr r3, [r3, #0]
8000b10: 1c5a adds r2, r3, #1
8000b12: 4b0d ldr r3, [pc, #52] ; (8000b48 <USART1_IRQHandler+0x120>)
8000b14: 601a str r2, [r3, #0]
break;
8000b16: e007 b.n 8000b28 <USART1_IRQHandler+0x100>
default:
rx_protocol_errors++;
8000b18: 4b0b ldr r3, [pc, #44] ; (8000b48 <USART1_IRQHandler+0x120>)
8000b1a: 681b ldr r3, [r3, #0]
8000b1c: 1c5a adds r2, r3, #1
8000b1e: 4b0a ldr r3, [pc, #40] ; (8000b48 <USART1_IRQHandler+0x120>)
8000b20: 601a str r2, [r3, #0]
}
return;
8000b22: e004 b.n 8000b2e <USART1_IRQHandler+0x106>
break;
8000b24: 46c0 nop ; (mov r8, r8)
8000b26: e002 b.n 8000b2e <USART1_IRQHandler+0x106>
break;
8000b28: 46c0 nop ; (mov r8, r8)
return;
8000b2a: e000 b.n 8000b2e <USART1_IRQHandler+0x106>
return;
8000b2c: 46c0 nop ; (mov r8, r8)
}
}
8000b2e: 46bd mov sp, r7
8000b30: b006 add sp, #24
8000b32: bd80 pop {r7, pc}
8000b34: 40013800 .word 0x40013800
8000b38: 2000013c .word 0x2000013c
8000b3c: 20000150 .word 0x20000150
8000b40: 20000148 .word 0x20000148
8000b44: 20000140 .word 0x20000140
8000b48: 20000144 .word 0x20000144
8000b4c: 20000198 .word 0x20000198
08000b50 <usart_schedule_dma>:
void usart_schedule_dma() {
8000b50: b580 push {r7, lr}
8000b52: b084 sub sp, #16
8000b54: af00 add r7, sp, #0
/* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ
* disables. */
volatile struct dma_tx_buf *buf = &usart_tx_buf;
8000b56: 4b19 ldr r3, [pc, #100] ; (8000bbc <usart_schedule_dma+0x6c>)
8000b58: 60bb str r3, [r7, #8]
ssize_t xfr_len, xfr_start = buf->xfr_end;
8000b5a: 68bb ldr r3, [r7, #8]
8000b5c: 685b ldr r3, [r3, #4]
8000b5e: 607b str r3, [r7, #4]
if (buf->wr_pos > xfr_start) /* no wraparound */
8000b60: 68bb ldr r3, [r7, #8]
8000b62: 689b ldr r3, [r3, #8]
8000b64: 687a ldr r2, [r7, #4]
8000b66: 429a cmp r2, r3
8000b68: da05 bge.n 8000b76 <usart_schedule_dma+0x26>
xfr_len = buf->wr_pos - xfr_start;
8000b6a: 68bb ldr r3, [r7, #8]
8000b6c: 689a ldr r2, [r3, #8]
8000b6e: 687b ldr r3, [r7, #4]
8000b70: 1ad3 subs r3, r2, r3
8000b72: 60fb str r3, [r7, #12]
8000b74: e004 b.n 8000b80 <usart_schedule_dma+0x30>
else /* wraparound */
xfr_len = sizeof(buf->data) - xfr_start; /* schedule transfer until end of buffer */
8000b76: 687b ldr r3, [r7, #4]
8000b78: 2280 movs r2, #128 ; 0x80
8000b7a: 0092 lsls r2, r2, #2
8000b7c: 1ad3 subs r3, r2, r3
8000b7e: 60fb str r3, [r7, #12]
buf->xfr_start = xfr_start;
8000b80: 68bb ldr r3, [r7, #8]
8000b82: 687a ldr r2, [r7, #4]
8000b84: 601a str r2, [r3, #0]
buf->xfr_end = (xfr_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
8000b86: 687a ldr r2, [r7, #4]
8000b88: 68fb ldr r3, [r7, #12]
8000b8a: 18d3 adds r3, r2, r3
8000b8c: 05db lsls r3, r3, #23
8000b8e: 0dda lsrs r2, r3, #23
8000b90: 68bb ldr r3, [r7, #8]
8000b92: 605a str r2, [r3, #4]
/* initiate transmission of new buffer */
DMA1_Channel2->CMAR = (uint32_t)(buf->data + xfr_start);
8000b94: 68bb ldr r3, [r7, #8]
8000b96: 3320 adds r3, #32
8000b98: 001a movs r2, r3
8000b9a: 687b ldr r3, [r7, #4]
8000b9c: 18d2 adds r2, r2, r3
8000b9e: 4b08 ldr r3, [pc, #32] ; (8000bc0 <usart_schedule_dma+0x70>)
8000ba0: 60da str r2, [r3, #12]
DMA1_Channel2->CNDTR = xfr_len;
8000ba2: 4b07 ldr r3, [pc, #28] ; (8000bc0 <usart_schedule_dma+0x70>)
8000ba4: 68fa ldr r2, [r7, #12]
8000ba6: 605a str r2, [r3, #4]
DMA1_Channel2->CCR |= DMA_CCR_EN;
8000ba8: 4b05 ldr r3, [pc, #20] ; (8000bc0 <usart_schedule_dma+0x70>)
8000baa: 681a ldr r2, [r3, #0]
8000bac: 4b04 ldr r3, [pc, #16] ; (8000bc0 <usart_schedule_dma+0x70>)
8000bae: 2101 movs r1, #1
8000bb0: 430a orrs r2, r1
8000bb2: 601a str r2, [r3, #0]
}
8000bb4: 46c0 nop ; (mov r8, r8)
8000bb6: 46bd mov sp, r7
8000bb8: b004 add sp, #16
8000bba: bd80 pop {r7, pc}
8000bbc: 20000198 .word 0x20000198
8000bc0: 4002001c .word 0x4002001c
08000bc4 <usart_ack_packet>:
int usart_ack_packet(uint8_t idx) {
8000bc4: b580 push {r7, lr}
8000bc6: b082 sub sp, #8
8000bc8: af00 add r7, sp, #0
8000bca: 0002 movs r2, r0
8000bcc: 1dfb adds r3, r7, #7
8000bce: 701a strb r2, [r3, #0]
if (idx > ARRAY_LEN(usart_tx_buf.packet_start))
8000bd0: 1dfb adds r3, r7, #7
8000bd2: 781b ldrb r3, [r3, #0]
8000bd4: 2b05 cmp r3, #5
8000bd6: d902 bls.n 8000bde <usart_ack_packet+0x1a>
return -EINVAL;
8000bd8: 2316 movs r3, #22
8000bda: 425b negs r3, r3
8000bdc: e00a b.n 8000bf4 <usart_ack_packet+0x30>
usart_tx_buf.packet_start[idx] = -1;
8000bde: 1dfb adds r3, r7, #7
8000be0: 781b ldrb r3, [r3, #0]
8000be2: 4a06 ldr r2, [pc, #24] ; (8000bfc <usart_ack_packet+0x38>)
8000be4: 3302 adds r3, #2
8000be6: 009b lsls r3, r3, #2
8000be8: 18d3 adds r3, r2, r3
8000bea: 3304 adds r3, #4
8000bec: 2201 movs r2, #1
8000bee: 4252 negs r2, r2
8000bf0: 601a str r2, [r3, #0]
return 0;
8000bf2: 2300 movs r3, #0
}
8000bf4: 0018 movs r0, r3
8000bf6: 46bd mov sp, r7
8000bf8: b002 add sp, #8
8000bfa: bd80 pop {r7, pc}
8000bfc: 20000198 .word 0x20000198
08000c00 <usart_dma_fifo_push>:
int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) {
8000c00: b580 push {r7, lr}
8000c02: b084 sub sp, #16
8000c04: af00 add r7, sp, #0
8000c06: 6078 str r0, [r7, #4]
8000c08: 000a movs r2, r1
8000c0a: 1cfb adds r3, r7, #3
8000c0c: 701a strb r2, [r3, #0]
/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
8000c0e: 200a movs r0, #10
8000c10: f7ff fe1a bl 8000848 <NVIC_DisableIRQ>
/* If the write pointer hit any unacknowledged packet start position we can't advance it.
* Packet start positions are unordered and we have to scan here. */
for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
8000c14: 2300 movs r3, #0
8000c16: 60fb str r3, [r7, #12]
8000c18: e013 b.n 8000c42 <usart_dma_fifo_push+0x42>
if (buf->wr_pos == buf->packet_start[i]) {
8000c1a: 687b ldr r3, [r7, #4]
8000c1c: 689a ldr r2, [r3, #8]
8000c1e: 6879 ldr r1, [r7, #4]
8000c20: 68fb ldr r3, [r7, #12]
8000c22: 3302 adds r3, #2
8000c24: 009b lsls r3, r3, #2
8000c26: 18cb adds r3, r1, r3
8000c28: 3304 adds r3, #4
8000c2a: 681b ldr r3, [r3, #0]
8000c2c: 429a cmp r2, r3
8000c2e: d105 bne.n 8000c3c <usart_dma_fifo_push+0x3c>
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
8000c30: 200a movs r0, #10
8000c32: f7ff fdf3 bl 800081c <NVIC_EnableIRQ>
return -EBUSY;
8000c36: 2310 movs r3, #16
8000c38: 425b negs r3, r3
8000c3a: e019 b.n 8000c70 <usart_dma_fifo_push+0x70>
for (size_t i=0; i<ARRAY_LEN(buf->packet_start); i++) {
8000c3c: 68fb ldr r3, [r7, #12]
8000c3e: 3301 adds r3, #1
8000c40: 60fb str r3, [r7, #12]
8000c42: 68fb ldr r3, [r7, #12]
8000c44: 2b04 cmp r3, #4
8000c46: d9e8 bls.n 8000c1a <usart_dma_fifo_push+0x1a>
}
}
/* write byte, then increment to avoid racing the DMA ISR reading wr_pos */
buf->data[buf->wr_pos] = c;
8000c48: 687b ldr r3, [r7, #4]
8000c4a: 689b ldr r3, [r3, #8]
8000c4c: 687a ldr r2, [r7, #4]
8000c4e: 2120 movs r1, #32
8000c50: 18d3 adds r3, r2, r3
8000c52: 185b adds r3, r3, r1
8000c54: 1cfa adds r2, r7, #3
8000c56: 7812 ldrb r2, [r2, #0]
8000c58: 701a strb r2, [r3, #0]
buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
8000c5a: 687b ldr r3, [r7, #4]
8000c5c: 689b ldr r3, [r3, #8]
8000c5e: 3301 adds r3, #1
8000c60: 05db lsls r3, r3, #23
8000c62: 0dda lsrs r2, r3, #23
8000c64: 687b ldr r3, [r7, #4]
8000c66: 609a str r2, [r3, #8]
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
8000c68: 200a movs r0, #10
8000c6a: f7ff fdd7 bl 800081c <NVIC_EnableIRQ>
return 0;
8000c6e: 2300 movs r3, #0
}
8000c70: 0018 movs r0, r3
8000c72: 46bd mov sp, r7
8000c74: b004 add sp, #16
8000c76: bd80 pop {r7, pc}
08000c78 <usart_putc>:
int usart_putc(uint8_t c) {
8000c78: b580 push {r7, lr}
8000c7a: b082 sub sp, #8
8000c7c: af00 add r7, sp, #0
8000c7e: 0002 movs r2, r0
8000c80: 1dfb adds r3, r7, #7
8000c82: 701a strb r2, [r3, #0]
/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
8000c84: 46c0 nop ; (mov r8, r8)
8000c86: 1dfb adds r3, r7, #7
8000c88: 781a ldrb r2, [r3, #0]
8000c8a: 4b06 ldr r3, [pc, #24] ; (8000ca4 <usart_putc+0x2c>)
8000c8c: 0011 movs r1, r2
8000c8e: 0018 movs r0, r3
8000c90: f7ff ffb6 bl 8000c00 <usart_dma_fifo_push>
8000c94: 0003 movs r3, r0
8000c96: 3310 adds r3, #16
8000c98: d0f5 beq.n 8000c86 <usart_putc+0xe>
/* idle */
}
return 0;
8000c9a: 2300 movs r3, #0
}
8000c9c: 0018 movs r0, r3
8000c9e: 46bd mov sp, r7
8000ca0: b002 add sp, #8
8000ca2: bd80 pop {r7, pc}
8000ca4: 20000198 .word 0x20000198
08000ca8 <usart_putc_nonblocking>:
int usart_putc_nonblocking(uint8_t c) {
8000ca8: b580 push {r7, lr}
8000caa: b082 sub sp, #8
8000cac: af00 add r7, sp, #0
8000cae: 0002 movs r2, r0
8000cb0: 1dfb adds r3, r7, #7
8000cb2: 701a strb r2, [r3, #0]
return usart_dma_fifo_push(&usart_tx_buf, c);
8000cb4: 1dfb adds r3, r7, #7
8000cb6: 781a ldrb r2, [r3, #0]
8000cb8: 4b04 ldr r3, [pc, #16] ; (8000ccc <usart_putc_nonblocking+0x24>)
8000cba: 0011 movs r1, r2
8000cbc: 0018 movs r0, r3
8000cbe: f7ff ff9f bl 8000c00 <usart_dma_fifo_push>
8000cc2: 0003 movs r3, r0
}
8000cc4: 0018 movs r0, r3
8000cc6: 46bd mov sp, r7
8000cc8: b002 add sp, #8
8000cca: bd80 pop {r7, pc}
8000ccc: 20000198 .word 0x20000198
08000cd0 <DMA1_Channel2_3_IRQHandler>:
void DMA1_Channel2_3_IRQHandler(void) {
8000cd0: b580 push {r7, lr}
8000cd2: af00 add r7, sp, #0
/* Transfer complete */
DMA1->IFCR |= DMA_IFCR_CTCIF2;
8000cd4: 4b0b ldr r3, [pc, #44] ; (8000d04 <DMA1_Channel2_3_IRQHandler+0x34>)
8000cd6: 685a ldr r2, [r3, #4]
8000cd8: 4b0a ldr r3, [pc, #40] ; (8000d04 <DMA1_Channel2_3_IRQHandler+0x34>)
8000cda: 2120 movs r1, #32
8000cdc: 430a orrs r2, r1
8000cde: 605a str r2, [r3, #4]
DMA1_Channel2->CCR &= ~DMA_CCR_EN;
8000ce0: 4b09 ldr r3, [pc, #36] ; (8000d08 <DMA1_Channel2_3_IRQHandler+0x38>)
8000ce2: 681a ldr r2, [r3, #0]
8000ce4: 4b08 ldr r3, [pc, #32] ; (8000d08 <DMA1_Channel2_3_IRQHandler+0x38>)
8000ce6: 2101 movs r1, #1
8000ce8: 438a bics r2, r1
8000cea: 601a str r2, [r3, #0]
if (usart_tx_buf.wr_pos != usart_tx_buf.xfr_end) /* buffer not empty */
8000cec: 4b07 ldr r3, [pc, #28] ; (8000d0c <DMA1_Channel2_3_IRQHandler+0x3c>)
8000cee: 689a ldr r2, [r3, #8]
8000cf0: 4b06 ldr r3, [pc, #24] ; (8000d0c <DMA1_Channel2_3_IRQHandler+0x3c>)
8000cf2: 685b ldr r3, [r3, #4]
8000cf4: 429a cmp r2, r3
8000cf6: d001 beq.n 8000cfc <DMA1_Channel2_3_IRQHandler+0x2c>
usart_schedule_dma();
8000cf8: f7ff ff2a bl 8000b50 <usart_schedule_dma>
}
8000cfc: 46c0 nop ; (mov r8, r8)
8000cfe: 46bd mov sp, r7
8000d00: bd80 pop {r7, pc}
8000d02: 46c0 nop ; (mov r8, r8)
8000d04: 40020000 .word 0x40020000
8000d08: 4002001c .word 0x4002001c
8000d0c: 20000198 .word 0x20000198
08000d10 <usart_retransmit_packet>:
int usart_retransmit_packet(uint8_t idx) {
8000d10: b590 push {r4, r7, lr}
8000d12: b087 sub sp, #28
8000d14: af00 add r7, sp, #0
8000d16: 0002 movs r2, r0
8000d18: 1dfb adds r3, r7, #7
8000d1a: 701a strb r2, [r3, #0]
/* Disable ADC DMA IRQ to prevent write races */
NVIC_DisableIRQ(DMA1_Channel1_IRQn);
8000d1c: 2009 movs r0, #9
8000d1e: f7ff fd93 bl 8000848 <NVIC_DisableIRQ>
ssize_t i = usart_tx_buf.packet_start[idx];
8000d22: 1dfb adds r3, r7, #7
8000d24: 781b ldrb r3, [r3, #0]
8000d26: 4a23 ldr r2, [pc, #140] ; (8000db4 <usart_retransmit_packet+0xa4>)
8000d28: 3302 adds r3, #2
8000d2a: 009b lsls r3, r3, #2
8000d2c: 18d3 adds r3, r2, r3
8000d2e: 3304 adds r3, #4
8000d30: 681b ldr r3, [r3, #0]
8000d32: 617b str r3, [r7, #20]
ssize_t start = i;
8000d34: 697b ldr r3, [r7, #20]
8000d36: 613b str r3, [r7, #16]
/* Copy packet */
uint8_t c;
while ((c = usart_tx_buf.data[i++])) {
8000d38: e00f b.n 8000d5a <usart_retransmit_packet+0x4a>
if (usart_putc_nonblocking(c)) {
8000d3a: 230f movs r3, #15
8000d3c: 18fb adds r3, r7, r3
8000d3e: 781b ldrb r3, [r3, #0]
8000d40: 0018 movs r0, r3
8000d42: f7ff ffb1 bl 8000ca8 <usart_putc_nonblocking>
8000d46: 1e03 subs r3, r0, #0
8000d48: d007 beq.n 8000d5a <usart_retransmit_packet+0x4a>
tx_overruns++;
8000d4a: 4b1b ldr r3, [pc, #108] ; (8000db8 <usart_retransmit_packet+0xa8>)
8000d4c: 681b ldr r3, [r3, #0]
8000d4e: 1c5a adds r2, r3, #1
8000d50: 4b19 ldr r3, [pc, #100] ; (8000db8 <usart_retransmit_packet+0xa8>)
8000d52: 601a str r2, [r3, #0]
return -EBUSY;
8000d54: 2310 movs r3, #16
8000d56: 425b negs r3, r3
8000d58: e028 b.n 8000dac <usart_retransmit_packet+0x9c>
while ((c = usart_tx_buf.data[i++])) {
8000d5a: 697b ldr r3, [r7, #20]
8000d5c: 1c5a adds r2, r3, #1
8000d5e: 617a str r2, [r7, #20]
8000d60: 240f movs r4, #15
8000d62: 193a adds r2, r7, r4
8000d64: 4913 ldr r1, [pc, #76] ; (8000db4 <usart_retransmit_packet+0xa4>)
8000d66: 2020 movs r0, #32
8000d68: 18cb adds r3, r1, r3
8000d6a: 181b adds r3, r3, r0
8000d6c: 781b ldrb r3, [r3, #0]
8000d6e: 7013 strb r3, [r2, #0]
8000d70: 193b adds r3, r7, r4
8000d72: 781b ldrb r3, [r3, #0]
8000d74: 2b00 cmp r3, #0
8000d76: d1e0 bne.n 8000d3a <usart_retransmit_packet+0x2a>
}
}
/* Terminating null byte */
if (usart_putc_nonblocking(0)) {
8000d78: 2000 movs r0, #0
8000d7a: f7ff ff95 bl 8000ca8 <usart_putc_nonblocking>
8000d7e: 1e03 subs r3, r0, #0
8000d80: d007 beq.n 8000d92 <usart_retransmit_packet+0x82>
tx_overruns++;
8000d82: 4b0d ldr r3, [pc, #52] ; (8000db8 <usart_retransmit_packet+0xa8>)
8000d84: 681b ldr r3, [r3, #0]
8000d86: 1c5a adds r2, r3, #1
8000d88: 4b0b ldr r3, [pc, #44] ; (8000db8 <usart_retransmit_packet+0xa8>)
8000d8a: 601a str r2, [r3, #0]
return -EBUSY;
8000d8c: 2310 movs r3, #16
8000d8e: 425b negs r3, r3
8000d90: e00c b.n 8000dac <usart_retransmit_packet+0x9c>
}
/* Update start index */
usart_tx_buf.packet_start[idx] = start;
8000d92: 1dfb adds r3, r7, #7
8000d94: 781b ldrb r3, [r3, #0]
8000d96: 4a07 ldr r2, [pc, #28] ; (8000db4 <usart_retransmit_packet+0xa4>)
8000d98: 3302 adds r3, #2
8000d9a: 009b lsls r3, r3, #2
8000d9c: 18d3 adds r3, r2, r3
8000d9e: 3304 adds r3, #4
8000da0: 693a ldr r2, [r7, #16]
8000da2: 601a str r2, [r3, #0]
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8000da4: 2009 movs r0, #9
8000da6: f7ff fd39 bl 800081c <NVIC_EnableIRQ>
return 0;
8000daa: 2300 movs r3, #0
}
8000dac: 0018 movs r0, r3
8000dae: 46bd mov sp, r7
8000db0: b007 add sp, #28
8000db2: bd90 pop {r4, r7, pc}
8000db4: 20000198 .word 0x20000198
8000db8: 20000138 .word 0x20000138
08000dbc <usart_send_packet_nonblocking>:
/* len is the packet length including headers */
int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
8000dbc: b590 push {r4, r7, lr}
8000dbe: b087 sub sp, #28
8000dc0: af00 add r7, sp, #0
8000dc2: 6078 str r0, [r7, #4]
8000dc4: 6039 str r1, [r7, #0]
ssize_t start = usart_tx_buf.wr_pos;
8000dc6: 4b40 ldr r3, [pc, #256] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
8000dc8: 689b ldr r3, [r3, #8]
8000dca: 60fb str r3, [r7, #12]
/* Find a free slot for this packet */
size_t packet_idx = 0;
8000dcc: 2300 movs r3, #0
8000dce: 617b str r3, [r7, #20]
do {
if (usart_tx_buf.packet_start[packet_idx] == -1)
8000dd0: 4a3d ldr r2, [pc, #244] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
8000dd2: 697b ldr r3, [r7, #20]
8000dd4: 3302 adds r3, #2
8000dd6: 009b lsls r3, r3, #2
8000dd8: 18d3 adds r3, r2, r3
8000dda: 3304 adds r3, #4
8000ddc: 681b ldr r3, [r3, #0]
8000dde: 3301 adds r3, #1
8000de0: d00d beq.n 8000dfe <usart_send_packet_nonblocking+0x42>
goto success;
} while (++packet_idx <ARRAY_LEN(usart_tx_buf.packet_start));
8000de2: 697b ldr r3, [r7, #20]
8000de4: 3301 adds r3, #1
8000de6: 617b str r3, [r7, #20]
8000de8: 697b ldr r3, [r7, #20]
8000dea: 2b04 cmp r3, #4
8000dec: d9f0 bls.n 8000dd0 <usart_send_packet_nonblocking+0x14>
tx_overruns++;
8000dee: 4b37 ldr r3, [pc, #220] ; (8000ecc <usart_send_packet_nonblocking+0x110>)
8000df0: 681b ldr r3, [r3, #0]
8000df2: 1c5a adds r2, r3, #1
8000df4: 4b35 ldr r3, [pc, #212] ; (8000ecc <usart_send_packet_nonblocking+0x110>)
8000df6: 601a str r2, [r3, #0]
return -EBUSY;
8000df8: 2310 movs r3, #16
8000dfa: 425b negs r3, r3
8000dfc: e060 b.n 8000ec0 <usart_send_packet_nonblocking+0x104>
goto success;
8000dfe: 46c0 nop ; (mov r8, r8)
success:
pkt->pid = packet_idx;
8000e00: 697b ldr r3, [r7, #20]
8000e02: b2da uxtb r2, r3
8000e04: 687b ldr r3, [r7, #4]
8000e06: 711a strb r2, [r3, #4]
/* make the value this wonky-ass CRC implementation produces match zlib etc. */
CRC->CR = CRC_CR_REV_OUT | (1<<CRC_CR_REV_IN_Pos) | CRC_CR_RESET;
8000e08: 4b31 ldr r3, [pc, #196] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
8000e0a: 22a1 movs r2, #161 ; 0xa1
8000e0c: 609a str r2, [r3, #8]
for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
8000e0e: 2304 movs r3, #4
8000e10: 613b str r3, [r7, #16]
8000e12: e008 b.n 8000e26 <usart_send_packet_nonblocking+0x6a>
CRC->DR = ((uint8_t *)pkt)[i];
8000e14: 687a ldr r2, [r7, #4]
8000e16: 693b ldr r3, [r7, #16]
8000e18: 18d3 adds r3, r2, r3
8000e1a: 781a ldrb r2, [r3, #0]
8000e1c: 4b2c ldr r3, [pc, #176] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
8000e1e: 601a str r2, [r3, #0]
for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
8000e20: 693b ldr r3, [r7, #16]
8000e22: 3301 adds r3, #1
8000e24: 613b str r3, [r7, #16]
8000e26: 693a ldr r2, [r7, #16]
8000e28: 683b ldr r3, [r7, #0]
8000e2a: 429a cmp r2, r3
8000e2c: d3f2 bcc.n 8000e14 <usart_send_packet_nonblocking+0x58>
pkt->crc32 = ~CRC->DR;
8000e2e: 4b28 ldr r3, [pc, #160] ; (8000ed0 <usart_send_packet_nonblocking+0x114>)
8000e30: 681b ldr r3, [r3, #0]
8000e32: 43da mvns r2, r3
8000e34: 687b ldr r3, [r7, #4]
8000e36: 21ff movs r1, #255 ; 0xff
8000e38: 4011 ands r1, r2
8000e3a: 000c movs r4, r1
8000e3c: 7819 ldrb r1, [r3, #0]
8000e3e: 2000 movs r0, #0
8000e40: 4001 ands r1, r0
8000e42: 1c08 adds r0, r1, #0
8000e44: 1c21 adds r1, r4, #0
8000e46: 4301 orrs r1, r0
8000e48: 7019 strb r1, [r3, #0]
8000e4a: 0a11 lsrs r1, r2, #8
8000e4c: 20ff movs r0, #255 ; 0xff
8000e4e: 4001 ands r1, r0
8000e50: 000c movs r4, r1
8000e52: 7859 ldrb r1, [r3, #1]
8000e54: 2000 movs r0, #0
8000e56: 4001 ands r1, r0
8000e58: 1c08 adds r0, r1, #0
8000e5a: 1c21 adds r1, r4, #0
8000e5c: 4301 orrs r1, r0
8000e5e: 7059 strb r1, [r3, #1]
8000e60: 0c11 lsrs r1, r2, #16
8000e62: 20ff movs r0, #255 ; 0xff
8000e64: 4001 ands r1, r0
8000e66: 000c movs r4, r1
8000e68: 7899 ldrb r1, [r3, #2]
8000e6a: 2000 movs r0, #0
8000e6c: 4001 ands r1, r0
8000e6e: 1c08 adds r0, r1, #0
8000e70: 1c21 adds r1, r4, #0
8000e72: 4301 orrs r1, r0
8000e74: 7099 strb r1, [r3, #2]
8000e76: 0e10 lsrs r0, r2, #24
8000e78: 78da ldrb r2, [r3, #3]
8000e7a: 2100 movs r1, #0
8000e7c: 400a ands r2, r1
8000e7e: 1c11 adds r1, r2, #0
8000e80: 1c02 adds r2, r0, #0
8000e82: 430a orrs r2, r1
8000e84: 70da strb r2, [r3, #3]
int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len);
8000e86: 683a ldr r2, [r7, #0]
8000e88: 6879 ldr r1, [r7, #4]
8000e8a: 4b12 ldr r3, [pc, #72] ; (8000ed4 <usart_send_packet_nonblocking+0x118>)
8000e8c: 0018 movs r0, r3
8000e8e: f000 f825 bl 8000edc <cobs_encode_usart>
8000e92: 0003 movs r3, r0
8000e94: 60bb str r3, [r7, #8]
if (rc)
8000e96: 68bb ldr r3, [r7, #8]
8000e98: 2b00 cmp r3, #0
8000e9a: d001 beq.n 8000ea0 <usart_send_packet_nonblocking+0xe4>
return rc;
8000e9c: 68bb ldr r3, [r7, #8]
8000e9e: e00f b.n 8000ec0 <usart_send_packet_nonblocking+0x104>
/* Checkpoint packet start index to prevent overwriting before ack */
usart_tx_buf.packet_start[packet_idx] = start;
8000ea0: 4a09 ldr r2, [pc, #36] ; (8000ec8 <usart_send_packet_nonblocking+0x10c>)
8000ea2: 697b ldr r3, [r7, #20]
8000ea4: 3302 adds r3, #2
8000ea6: 009b lsls r3, r3, #2
8000ea8: 18d3 adds r3, r2, r3
8000eaa: 3304 adds r3, #4
8000eac: 68fa ldr r2, [r7, #12]
8000eae: 601a str r2, [r3, #0]
for (size_t i=0; i<351; i++)
usart_putc_nonblocking(x++);
*/
/* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
8000eb0: 4b09 ldr r3, [pc, #36] ; (8000ed8 <usart_send_packet_nonblocking+0x11c>)
8000eb2: 681b ldr r3, [r3, #0]
8000eb4: 2201 movs r2, #1
8000eb6: 4013 ands r3, r2
8000eb8: d101 bne.n 8000ebe <usart_send_packet_nonblocking+0x102>
usart_schedule_dma();
8000eba: f7ff fe49 bl 8000b50 <usart_schedule_dma>
return 0;
8000ebe: 2300 movs r3, #0
}
8000ec0: 0018 movs r0, r3
8000ec2: 46bd mov sp, r7
8000ec4: b007 add sp, #28
8000ec6: bd90 pop {r4, r7, pc}
8000ec8: 20000198 .word 0x20000198
8000ecc: 20000138 .word 0x20000138
8000ed0: 40023000 .word 0x40023000
8000ed4: 08000ca9 .word 0x08000ca9
8000ed8: 4002001c .word 0x4002001c
08000edc <cobs_encode_usart>:
#include "serial.h"
#include "cobs.h"
int cobs_encode_usart(int (*output)(char), char *src, size_t srclen) {
8000edc: b580 push {r7, lr}
8000ede: b08a sub sp, #40 ; 0x28
8000ee0: af00 add r7, sp, #0
8000ee2: 60f8 str r0, [r7, #12]
8000ee4: 60b9 str r1, [r7, #8]
8000ee6: 607a str r2, [r7, #4]
if (srclen > 254)
8000ee8: 687b ldr r3, [r7, #4]
8000eea: 2bfe cmp r3, #254 ; 0xfe
8000eec: d902 bls.n 8000ef4 <cobs_encode_usart+0x18>
return -1;
8000eee: 2301 movs r3, #1
8000ef0: 425b negs r3, r3
8000ef2: e04e b.n 8000f92 <cobs_encode_usart+0xb6>
size_t p = 0;
8000ef4: 2300 movs r3, #0
8000ef6: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
8000ef8: e03c b.n 8000f74 <cobs_encode_usart+0x98>
char val;
if (p != 0 && src[p-1] != 0) {
8000efa: 6a7b ldr r3, [r7, #36] ; 0x24
8000efc: 2b00 cmp r3, #0
8000efe: d00f beq.n 8000f20 <cobs_encode_usart+0x44>
8000f00: 6a7b ldr r3, [r7, #36] ; 0x24
8000f02: 3b01 subs r3, #1
8000f04: 68ba ldr r2, [r7, #8]
8000f06: 18d3 adds r3, r2, r3
8000f08: 781b ldrb r3, [r3, #0]
8000f0a: 2b00 cmp r3, #0
8000f0c: d008 beq.n 8000f20 <cobs_encode_usart+0x44>
val = src[p-1];
8000f0e: 6a7b ldr r3, [r7, #36] ; 0x24
8000f10: 3b01 subs r3, #1
8000f12: 68ba ldr r2, [r7, #8]
8000f14: 18d2 adds r2, r2, r3
8000f16: 2323 movs r3, #35 ; 0x23
8000f18: 18fb adds r3, r7, r3
8000f1a: 7812 ldrb r2, [r2, #0]
8000f1c: 701a strb r2, [r3, #0]
8000f1e: e019 b.n 8000f54 <cobs_encode_usart+0x78>
} else {
size_t q = p;
8000f20: 6a7b ldr r3, [r7, #36] ; 0x24
8000f22: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
8000f24: e002 b.n 8000f2c <cobs_encode_usart+0x50>
q++;
8000f26: 69fb ldr r3, [r7, #28]
8000f28: 3301 adds r3, #1
8000f2a: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
8000f2c: 69fa ldr r2, [r7, #28]
8000f2e: 687b ldr r3, [r7, #4]
8000f30: 429a cmp r2, r3
8000f32: d205 bcs.n 8000f40 <cobs_encode_usart+0x64>
8000f34: 68ba ldr r2, [r7, #8]
8000f36: 69fb ldr r3, [r7, #28]
8000f38: 18d3 adds r3, r2, r3
8000f3a: 781b ldrb r3, [r3, #0]
8000f3c: 2b00 cmp r3, #0
8000f3e: d1f2 bne.n 8000f26 <cobs_encode_usart+0x4a>
val = (char)q-p+1;
8000f40: 69fb ldr r3, [r7, #28]
8000f42: b2da uxtb r2, r3
8000f44: 6a7b ldr r3, [r7, #36] ; 0x24
8000f46: b2db uxtb r3, r3
8000f48: 1ad3 subs r3, r2, r3
8000f4a: b2da uxtb r2, r3
8000f4c: 2323 movs r3, #35 ; 0x23
8000f4e: 18fb adds r3, r7, r3
8000f50: 3201 adds r2, #1
8000f52: 701a strb r2, [r3, #0]
}
int rv = output(val);
8000f54: 2323 movs r3, #35 ; 0x23
8000f56: 18fb adds r3, r7, r3
8000f58: 781a ldrb r2, [r3, #0]
8000f5a: 68fb ldr r3, [r7, #12]
8000f5c: 0010 movs r0, r2
8000f5e: 4798 blx r3
8000f60: 0003 movs r3, r0
8000f62: 617b str r3, [r7, #20]
if (rv)
8000f64: 697b ldr r3, [r7, #20]
8000f66: 2b00 cmp r3, #0
8000f68: d001 beq.n 8000f6e <cobs_encode_usart+0x92>
return rv;
8000f6a: 697b ldr r3, [r7, #20]
8000f6c: e011 b.n 8000f92 <cobs_encode_usart+0xb6>
p++;
8000f6e: 6a7b ldr r3, [r7, #36] ; 0x24
8000f70: 3301 adds r3, #1
8000f72: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
8000f74: 6a7a ldr r2, [r7, #36] ; 0x24
8000f76: 687b ldr r3, [r7, #4]
8000f78: 429a cmp r2, r3
8000f7a: d9be bls.n 8000efa <cobs_encode_usart+0x1e>
}
int rv = output(0);
8000f7c: 68fb ldr r3, [r7, #12]
8000f7e: 2000 movs r0, #0
8000f80: 4798 blx r3
8000f82: 0003 movs r3, r0
8000f84: 61bb str r3, [r7, #24]
if (rv)
8000f86: 69bb ldr r3, [r7, #24]
8000f88: 2b00 cmp r3, #0
8000f8a: d001 beq.n 8000f90 <cobs_encode_usart+0xb4>
return rv;
8000f8c: 69bb ldr r3, [r7, #24]
8000f8e: e000 b.n 8000f92 <cobs_encode_usart+0xb6>
return 0;
8000f90: 2300 movs r3, #0
}
8000f92: 0018 movs r0, r3
8000f94: 46bd mov sp, r7
8000f96: b00a add sp, #40 ; 0x28
8000f98: bd80 pop {r7, pc}
08000f9a <cobs_decode>:
@ ensures \result == -1;
@
@ complete behaviors;
@ disjoint behaviors;
@*/
ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen) {
8000f9a: b580 push {r7, lr}
8000f9c: b088 sub sp, #32
8000f9e: af00 add r7, sp, #0
8000fa0: 60f8 str r0, [r7, #12]
8000fa2: 60b9 str r1, [r7, #8]
8000fa4: 607a str r2, [r7, #4]
8000fa6: 603b str r3, [r7, #0]
if (dstlen > 65535 || srclen > 65535)
8000fa8: 68ba ldr r2, [r7, #8]
8000faa: 2380 movs r3, #128 ; 0x80
8000fac: 025b lsls r3, r3, #9
8000fae: 429a cmp r2, r3
8000fb0: d204 bcs.n 8000fbc <cobs_decode+0x22>
8000fb2: 683a ldr r2, [r7, #0]
8000fb4: 2380 movs r3, #128 ; 0x80
8000fb6: 025b lsls r3, r3, #9
8000fb8: 429a cmp r2, r3
8000fba: d302 bcc.n 8000fc2 <cobs_decode+0x28>
return -1;
8000fbc: 2301 movs r3, #1
8000fbe: 425b negs r3, r3
8000fc0: e052 b.n 8001068 <cobs_decode+0xce>
if (srclen < 1)
8000fc2: 683b ldr r3, [r7, #0]
8000fc4: 2b00 cmp r3, #0
8000fc6: d102 bne.n 8000fce <cobs_decode+0x34>
return -1;
8000fc8: 2301 movs r3, #1
8000fca: 425b negs r3, r3
8000fcc: e04c b.n 8001068 <cobs_decode+0xce>
if (dstlen < srclen)
8000fce: 68ba ldr r2, [r7, #8]
8000fd0: 683b ldr r3, [r7, #0]
8000fd2: 429a cmp r2, r3
8000fd4: d202 bcs.n 8000fdc <cobs_decode+0x42>
return -1;
8000fd6: 2301 movs r3, #1
8000fd8: 425b negs r3, r3
8000fda: e045 b.n 8001068 <cobs_decode+0xce>
size_t p = 1;
8000fdc: 2301 movs r3, #1
8000fde: 61fb str r3, [r7, #28]
size_t c = (unsigned char)src[0];
8000fe0: 687b ldr r3, [r7, #4]
8000fe2: 781b ldrb r3, [r3, #0]
8000fe4: 61bb str r3, [r7, #24]
//@ assert 0 <= c < 256;
//@ assert 0 <= c;
//@ assert c < 256;
if (c == 0)
8000fe6: 69bb ldr r3, [r7, #24]
8000fe8: 2b00 cmp r3, #0
8000fea: d124 bne.n 8001036 <cobs_decode+0x9c>
return -2; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
8000fec: 2302 movs r3, #2
8000fee: 425b negs r3, r3
8000ff0: e03a b.n 8001068 <cobs_decode+0xce>
@ loop assigns dst[0..dstlen-1], p, c;
@ loop variant srclen-p;
@*/
while (p < srclen && src[p]) {
char val;
c--;
8000ff2: 69bb ldr r3, [r7, #24]
8000ff4: 3b01 subs r3, #1
8000ff6: 61bb str r3, [r7, #24]
//@ assert src[p] != 0;
if (c == 0) {
8000ff8: 69bb ldr r3, [r7, #24]
8000ffa: 2b00 cmp r3, #0
8000ffc: d109 bne.n 8001012 <cobs_decode+0x78>
c = (unsigned char)src[p];
8000ffe: 687a ldr r2, [r7, #4]
8001000: 69fb ldr r3, [r7, #28]
8001002: 18d3 adds r3, r2, r3
8001004: 781b ldrb r3, [r3, #0]
8001006: 61bb str r3, [r7, #24]
val = 0;
8001008: 2317 movs r3, #23
800100a: 18fb adds r3, r7, r3
800100c: 2200 movs r2, #0
800100e: 701a strb r2, [r3, #0]
8001010: e006 b.n 8001020 <cobs_decode+0x86>
} else {
val = src[p];
8001012: 687a ldr r2, [r7, #4]
8001014: 69fb ldr r3, [r7, #28]
8001016: 18d2 adds r2, r2, r3
8001018: 2317 movs r3, #23
800101a: 18fb adds r3, r7, r3
800101c: 7812 ldrb r2, [r2, #0]
800101e: 701a strb r2, [r3, #0]
}
//@ assert 0 <= p-1 <= dstlen-1;
dst[p-1] = val;
8001020: 69fb ldr r3, [r7, #28]
8001022: 3b01 subs r3, #1
8001024: 68fa ldr r2, [r7, #12]
8001026: 18d3 adds r3, r2, r3
8001028: 2217 movs r2, #23
800102a: 18ba adds r2, r7, r2
800102c: 7812 ldrb r2, [r2, #0]
800102e: 701a strb r2, [r3, #0]
p++;
8001030: 69fb ldr r3, [r7, #28]
8001032: 3301 adds r3, #1
8001034: 61fb str r3, [r7, #28]
while (p < srclen && src[p]) {
8001036: 69fa ldr r2, [r7, #28]
8001038: 683b ldr r3, [r7, #0]
800103a: 429a cmp r2, r3
800103c: d205 bcs.n 800104a <cobs_decode+0xb0>
800103e: 687a ldr r2, [r7, #4]
8001040: 69fb ldr r3, [r7, #28]
8001042: 18d3 adds r3, r2, r3
8001044: 781b ldrb r3, [r3, #0]
8001046: 2b00 cmp r3, #0
8001048: d1d3 bne.n 8000ff2 <cobs_decode+0x58>
}
if (p == srclen)
800104a: 69fa ldr r2, [r7, #28]
800104c: 683b ldr r3, [r7, #0]
800104e: 429a cmp r2, r3
8001050: d102 bne.n 8001058 <cobs_decode+0xbe>
return -2; /* Invalid framing. The terminating null byte should always be present in the input buffer. */
8001052: 2302 movs r3, #2
8001054: 425b negs r3, r3
8001056: e007 b.n 8001068 <cobs_decode+0xce>
if (c != 1)
8001058: 69bb ldr r3, [r7, #24]
800105a: 2b01 cmp r3, #1
800105c: d002 beq.n 8001064 <cobs_decode+0xca>
return -3; /* Invalid framing. The skip counter does not hit the end of the frame. */
800105e: 2303 movs r3, #3
8001060: 425b negs r3, r3
8001062: e001 b.n 8001068 <cobs_decode+0xce>
//@ assert 0 < p <= srclen <= 65535;
//@ assert src[p] == 0;
//@ assert \forall integer i; 1 <= i < p ==> src[i] != 0;
return p-1;
8001064: 69fb ldr r3, [r7, #28]
8001066: 3b01 subs r3, #1
}
8001068: 0018 movs r0, r3
800106a: 46bd mov sp, r7
800106c: b008 add sp, #32
800106e: bd80 pop {r7, pc}
08001070 <cobs_decode_incremental_initialize>:
void cobs_decode_incremental_initialize(struct cobs_decode_state *state) {
8001070: b580 push {r7, lr}
8001072: b082 sub sp, #8
8001074: af00 add r7, sp, #0
8001076: 6078 str r0, [r7, #4]
state->p = 0;
8001078: 687b ldr r3, [r7, #4]
800107a: 2200 movs r2, #0
800107c: 601a str r2, [r3, #0]
state->c = 0;
800107e: 687b ldr r3, [r7, #4]
8001080: 2200 movs r2, #0
8001082: 605a str r2, [r3, #4]
}
8001084: 46c0 nop ; (mov r8, r8)
8001086: 46bd mov sp, r7
8001088: b002 add sp, #8
800108a: bd80 pop {r7, pc}
0800108c <cobs_decode_incremental>:
int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src) {
800108c: b580 push {r7, lr}
800108e: b088 sub sp, #32
8001090: af00 add r7, sp, #0
8001092: 60f8 str r0, [r7, #12]
8001094: 60b9 str r1, [r7, #8]
8001096: 607a str r2, [r7, #4]
8001098: 001a movs r2, r3
800109a: 1cfb adds r3, r7, #3
800109c: 701a strb r2, [r3, #0]
if (state->p == 0) {
800109e: 68fb ldr r3, [r7, #12]
80010a0: 681b ldr r3, [r3, #0]
80010a2: 2b00 cmp r3, #0
80010a4: d10e bne.n 80010c4 <cobs_decode_incremental+0x38>
if (src == 0)
80010a6: 1cfb adds r3, r7, #3
80010a8: 781b ldrb r3, [r3, #0]
80010aa: 2b00 cmp r3, #0
80010ac: d054 beq.n 8001158 <cobs_decode_incremental+0xcc>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
state->c = (unsigned char)src;
80010ae: 1cfb adds r3, r7, #3
80010b0: 781a ldrb r2, [r3, #0]
80010b2: 68fb ldr r3, [r7, #12]
80010b4: 605a str r2, [r3, #4]
state->p++;
80010b6: 68fb ldr r3, [r7, #12]
80010b8: 681b ldr r3, [r3, #0]
80010ba: 1c5a adds r2, r3, #1
80010bc: 68fb ldr r3, [r7, #12]
80010be: 601a str r2, [r3, #0]
return 0;
80010c0: 2300 movs r3, #0
80010c2: e050 b.n 8001166 <cobs_decode_incremental+0xda>
}
if (!src) {
80010c4: 1cfb adds r3, r7, #3
80010c6: 781b ldrb r3, [r3, #0]
80010c8: 2b00 cmp r3, #0
80010ca: d10d bne.n 80010e8 <cobs_decode_incremental+0x5c>
if (state->c != 1)
80010cc: 68fb ldr r3, [r7, #12]
80010ce: 685b ldr r3, [r3, #4]
80010d0: 2b01 cmp r3, #1
80010d2: d139 bne.n 8001148 <cobs_decode_incremental+0xbc>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
int rv = state->p-1;
80010d4: 68fb ldr r3, [r7, #12]
80010d6: 681b ldr r3, [r3, #0]
80010d8: 3b01 subs r3, #1
80010da: 617b str r3, [r7, #20]
cobs_decode_incremental_initialize(state);
80010dc: 68fb ldr r3, [r7, #12]
80010de: 0018 movs r0, r3
80010e0: f7ff ffc6 bl 8001070 <cobs_decode_incremental_initialize>
return rv;
80010e4: 697b ldr r3, [r7, #20]
80010e6: e03e b.n 8001166 <cobs_decode_incremental+0xda>
}
char val;
state->c--;
80010e8: 68fb ldr r3, [r7, #12]
80010ea: 685b ldr r3, [r3, #4]
80010ec: 1e5a subs r2, r3, #1
80010ee: 68fb ldr r3, [r7, #12]
80010f0: 605a str r2, [r3, #4]
if (state->c == 0) {
80010f2: 68fb ldr r3, [r7, #12]
80010f4: 685b ldr r3, [r3, #4]
80010f6: 2b00 cmp r3, #0
80010f8: d108 bne.n 800110c <cobs_decode_incremental+0x80>
state->c = (unsigned char)src;
80010fa: 1cfb adds r3, r7, #3
80010fc: 781a ldrb r2, [r3, #0]
80010fe: 68fb ldr r3, [r7, #12]
8001100: 605a str r2, [r3, #4]
val = 0;
8001102: 231f movs r3, #31
8001104: 18fb adds r3, r7, r3
8001106: 2200 movs r2, #0
8001108: 701a strb r2, [r3, #0]
800110a: e004 b.n 8001116 <cobs_decode_incremental+0x8a>
} else {
val = src;
800110c: 231f movs r3, #31
800110e: 18fb adds r3, r7, r3
8001110: 1cfa adds r2, r7, #3
8001112: 7812 ldrb r2, [r2, #0]
8001114: 701a strb r2, [r3, #0]
}
size_t pos = state->p-1;
8001116: 68fb ldr r3, [r7, #12]
8001118: 681b ldr r3, [r3, #0]
800111a: 3b01 subs r3, #1
800111c: 61bb str r3, [r7, #24]
if (pos >= dstlen)
800111e: 69ba ldr r2, [r7, #24]
8001120: 687b ldr r3, [r7, #4]
8001122: 429a cmp r2, r3
8001124: d302 bcc.n 800112c <cobs_decode_incremental+0xa0>
return -2; /* output buffer too small */
8001126: 2302 movs r3, #2
8001128: 425b negs r3, r3
800112a: e01c b.n 8001166 <cobs_decode_incremental+0xda>
dst[pos] = val;
800112c: 68ba ldr r2, [r7, #8]
800112e: 69bb ldr r3, [r7, #24]
8001130: 18d3 adds r3, r2, r3
8001132: 221f movs r2, #31
8001134: 18ba adds r2, r7, r2
8001136: 7812 ldrb r2, [r2, #0]
8001138: 701a strb r2, [r3, #0]
state->p++;
800113a: 68fb ldr r3, [r7, #12]
800113c: 681b ldr r3, [r3, #0]
800113e: 1c5a adds r2, r3, #1
8001140: 68fb ldr r3, [r7, #12]
8001142: 601a str r2, [r3, #0]
return 0;
8001144: 2300 movs r3, #0
8001146: e00e b.n 8001166 <cobs_decode_incremental+0xda>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
8001148: 46c0 nop ; (mov r8, r8)
errout:
cobs_decode_incremental_initialize(state);
800114a: 68fb ldr r3, [r7, #12]
800114c: 0018 movs r0, r3
800114e: f7ff ff8f bl 8001070 <cobs_decode_incremental_initialize>
return -1;
8001152: 2301 movs r3, #1
8001154: 425b negs r3, r3
8001156: e006 b.n 8001166 <cobs_decode_incremental+0xda>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
8001158: 46c0 nop ; (mov r8, r8)
empty_errout:
cobs_decode_incremental_initialize(state);
800115a: 68fb ldr r3, [r7, #12]
800115c: 0018 movs r0, r3
800115e: f7ff ff87 bl 8001070 <cobs_decode_incremental_initialize>
return -3;
8001162: 2303 movs r3, #3
8001164: 425b negs r3, r3
}
8001166: 0018 movs r0, r3
8001168: 46bd mov sp, r7
800116a: b008 add sp, #32
800116c: bd80 pop {r7, pc}
800116e: 1c64 .short 0x1c64
8001170: 00000800 .word 0x00000800
8001174: 00942000 .word 0x00942000
8001178: 00942000 .word 0x00942000
800117c: 03b82000 .word 0x03b82000
8001180: 00002000 .word 0x00002000
08001184 <SystemInit>:
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
8001184: b580 push {r7, lr}
8001186: af00 add r7, sp, #0
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001U;
8001188: 4b1a ldr r3, [pc, #104] ; (80011f4 <SystemInit+0x70>)
800118a: 681a ldr r2, [r3, #0]
800118c: 4b19 ldr r3, [pc, #100] ; (80011f4 <SystemInit+0x70>)
800118e: 2101 movs r1, #1
8001190: 430a orrs r2, r1
8001192: 601a str r2, [r3, #0]
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80CU;
8001194: 4b17 ldr r3, [pc, #92] ; (80011f4 <SystemInit+0x70>)
8001196: 685a ldr r2, [r3, #4]
8001198: 4b16 ldr r3, [pc, #88] ; (80011f4 <SystemInit+0x70>)
800119a: 4917 ldr r1, [pc, #92] ; (80011f8 <SystemInit+0x74>)
800119c: 400a ands r2, r1
800119e: 605a str r2, [r3, #4]
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFFU;
80011a0: 4b14 ldr r3, [pc, #80] ; (80011f4 <SystemInit+0x70>)
80011a2: 681a ldr r2, [r3, #0]
80011a4: 4b13 ldr r3, [pc, #76] ; (80011f4 <SystemInit+0x70>)
80011a6: 4915 ldr r1, [pc, #84] ; (80011fc <SystemInit+0x78>)
80011a8: 400a ands r2, r1
80011aa: 601a str r2, [r3, #0]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFFU;
80011ac: 4b11 ldr r3, [pc, #68] ; (80011f4 <SystemInit+0x70>)
80011ae: 681a ldr r2, [r3, #0]
80011b0: 4b10 ldr r3, [pc, #64] ; (80011f4 <SystemInit+0x70>)
80011b2: 4913 ldr r1, [pc, #76] ; (8001200 <SystemInit+0x7c>)
80011b4: 400a ands r2, r1
80011b6: 601a str r2, [r3, #0]
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
80011b8: 4b0e ldr r3, [pc, #56] ; (80011f4 <SystemInit+0x70>)
80011ba: 685a ldr r2, [r3, #4]
80011bc: 4b0d ldr r3, [pc, #52] ; (80011f4 <SystemInit+0x70>)
80011be: 4911 ldr r1, [pc, #68] ; (8001204 <SystemInit+0x80>)
80011c0: 400a ands r2, r1
80011c2: 605a str r2, [r3, #4]
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
80011c4: 4b0b ldr r3, [pc, #44] ; (80011f4 <SystemInit+0x70>)
80011c6: 6ada ldr r2, [r3, #44] ; 0x2c
80011c8: 4b0a ldr r3, [pc, #40] ; (80011f4 <SystemInit+0x70>)
80011ca: 210f movs r1, #15
80011cc: 438a bics r2, r1
80011ce: 62da str r2, [r3, #44] ; 0x2c
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
80011d0: 4b08 ldr r3, [pc, #32] ; (80011f4 <SystemInit+0x70>)
80011d2: 6b1a ldr r2, [r3, #48] ; 0x30
80011d4: 4b07 ldr r3, [pc, #28] ; (80011f4 <SystemInit+0x70>)
80011d6: 490c ldr r1, [pc, #48] ; (8001208 <SystemInit+0x84>)
80011d8: 400a ands r2, r1
80011da: 631a str r2, [r3, #48] ; 0x30
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
80011dc: 4b05 ldr r3, [pc, #20] ; (80011f4 <SystemInit+0x70>)
80011de: 6b5a ldr r2, [r3, #52] ; 0x34
80011e0: 4b04 ldr r3, [pc, #16] ; (80011f4 <SystemInit+0x70>)
80011e2: 2101 movs r1, #1
80011e4: 438a bics r2, r1
80011e6: 635a str r2, [r3, #52] ; 0x34
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
80011e8: 4b02 ldr r3, [pc, #8] ; (80011f4 <SystemInit+0x70>)
80011ea: 2200 movs r2, #0
80011ec: 609a str r2, [r3, #8]
}
80011ee: 46c0 nop ; (mov r8, r8)
80011f0: 46bd mov sp, r7
80011f2: bd80 pop {r7, pc}
80011f4: 40021000 .word 0x40021000
80011f8: 08ffb80c .word 0x08ffb80c
80011fc: fef6ffff .word 0xfef6ffff
8001200: fffbffff .word 0xfffbffff
8001204: ffc0ffff .word 0xffc0ffff
8001208: fffffeec .word 0xfffffeec
0800120c <SystemCoreClockUpdate>:
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
800120c: b580 push {r7, lr}
800120e: b084 sub sp, #16
8001210: af00 add r7, sp, #0
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
8001212: 2300 movs r3, #0
8001214: 60fb str r3, [r7, #12]
8001216: 2300 movs r3, #0
8001218: 60bb str r3, [r7, #8]
800121a: 2300 movs r3, #0
800121c: 607b str r3, [r7, #4]
800121e: 2300 movs r3, #0
8001220: 603b str r3, [r7, #0]
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
8001222: 4b31 ldr r3, [pc, #196] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
8001224: 685b ldr r3, [r3, #4]
8001226: 220c movs r2, #12
8001228: 4013 ands r3, r2
800122a: 60fb str r3, [r7, #12]
switch (tmp)
800122c: 68fb ldr r3, [r7, #12]
800122e: 2b08 cmp r3, #8
8001230: d011 beq.n 8001256 <SystemCoreClockUpdate+0x4a>
8001232: 68fb ldr r3, [r7, #12]
8001234: 2b08 cmp r3, #8
8001236: d841 bhi.n 80012bc <SystemCoreClockUpdate+0xb0>
8001238: 68fb ldr r3, [r7, #12]
800123a: 2b00 cmp r3, #0
800123c: d003 beq.n 8001246 <SystemCoreClockUpdate+0x3a>
800123e: 68fb ldr r3, [r7, #12]
8001240: 2b04 cmp r3, #4
8001242: d004 beq.n 800124e <SystemCoreClockUpdate+0x42>
8001244: e03a b.n 80012bc <SystemCoreClockUpdate+0xb0>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
8001246: 4b29 ldr r3, [pc, #164] ; (80012ec <SystemCoreClockUpdate+0xe0>)
8001248: 4a29 ldr r2, [pc, #164] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
800124a: 601a str r2, [r3, #0]
break;
800124c: e03a b.n 80012c4 <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
800124e: 4b27 ldr r3, [pc, #156] ; (80012ec <SystemCoreClockUpdate+0xe0>)
8001250: 4a27 ldr r2, [pc, #156] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
8001252: 601a str r2, [r3, #0]
break;
8001254: e036 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
8001256: 4b24 ldr r3, [pc, #144] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
8001258: 685a ldr r2, [r3, #4]
800125a: 23f0 movs r3, #240 ; 0xf0
800125c: 039b lsls r3, r3, #14
800125e: 4013 ands r3, r2
8001260: 60bb str r3, [r7, #8]
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
8001262: 4b21 ldr r3, [pc, #132] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
8001264: 685a ldr r2, [r3, #4]
8001266: 2380 movs r3, #128 ; 0x80
8001268: 025b lsls r3, r3, #9
800126a: 4013 ands r3, r2
800126c: 607b str r3, [r7, #4]
pllmull = ( pllmull >> 18) + 2;
800126e: 68bb ldr r3, [r7, #8]
8001270: 0c9b lsrs r3, r3, #18
8001272: 3302 adds r3, #2
8001274: 60bb str r3, [r7, #8]
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
8001276: 4b1c ldr r3, [pc, #112] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
8001278: 6adb ldr r3, [r3, #44] ; 0x2c
800127a: 220f movs r2, #15
800127c: 4013 ands r3, r2
800127e: 3301 adds r3, #1
8001280: 603b str r3, [r7, #0]
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
8001282: 687a ldr r2, [r7, #4]
8001284: 2380 movs r3, #128 ; 0x80
8001286: 025b lsls r3, r3, #9
8001288: 429a cmp r2, r3
800128a: d10a bne.n 80012a2 <SystemCoreClockUpdate+0x96>
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
800128c: 6839 ldr r1, [r7, #0]
800128e: 4818 ldr r0, [pc, #96] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
8001290: f000 fb3e bl 8001910 <__udivsi3>
8001294: 0003 movs r3, r0
8001296: 001a movs r2, r3
8001298: 68bb ldr r3, [r7, #8]
800129a: 435a muls r2, r3
800129c: 4b13 ldr r3, [pc, #76] ; (80012ec <SystemCoreClockUpdate+0xe0>)
800129e: 601a str r2, [r3, #0]
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
80012a0: e010 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
80012a2: 68b9 ldr r1, [r7, #8]
80012a4: 000a movs r2, r1
80012a6: 0152 lsls r2, r2, #5
80012a8: 1a52 subs r2, r2, r1
80012aa: 0193 lsls r3, r2, #6
80012ac: 1a9b subs r3, r3, r2
80012ae: 00db lsls r3, r3, #3
80012b0: 185b adds r3, r3, r1
80012b2: 021b lsls r3, r3, #8
80012b4: 001a movs r2, r3
80012b6: 4b0d ldr r3, [pc, #52] ; (80012ec <SystemCoreClockUpdate+0xe0>)
80012b8: 601a str r2, [r3, #0]
break;
80012ba: e003 b.n 80012c4 <SystemCoreClockUpdate+0xb8>
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
80012bc: 4b0b ldr r3, [pc, #44] ; (80012ec <SystemCoreClockUpdate+0xe0>)
80012be: 4a0c ldr r2, [pc, #48] ; (80012f0 <SystemCoreClockUpdate+0xe4>)
80012c0: 601a str r2, [r3, #0]
break;
80012c2: 46c0 nop ; (mov r8, r8)
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
80012c4: 4b08 ldr r3, [pc, #32] ; (80012e8 <SystemCoreClockUpdate+0xdc>)
80012c6: 685b ldr r3, [r3, #4]
80012c8: 091b lsrs r3, r3, #4
80012ca: 220f movs r2, #15
80012cc: 4013 ands r3, r2
80012ce: 4a09 ldr r2, [pc, #36] ; (80012f4 <SystemCoreClockUpdate+0xe8>)
80012d0: 5cd3 ldrb r3, [r2, r3]
80012d2: 60fb str r3, [r7, #12]
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
80012d4: 4b05 ldr r3, [pc, #20] ; (80012ec <SystemCoreClockUpdate+0xe0>)
80012d6: 681a ldr r2, [r3, #0]
80012d8: 68fb ldr r3, [r7, #12]
80012da: 40da lsrs r2, r3
80012dc: 4b03 ldr r3, [pc, #12] ; (80012ec <SystemCoreClockUpdate+0xe0>)
80012de: 601a str r2, [r3, #0]
}
80012e0: 46c0 nop ; (mov r8, r8)
80012e2: 46bd mov sp, r7
80012e4: b004 add sp, #16
80012e6: bd80 pop {r7, pc}
80012e8: 40021000 .word 0x40021000
80012ec: 20000000 .word 0x20000000
80012f0: 007a1200 .word 0x007a1200
80012f4: 08001c4c .word 0x08001c4c
080012f8 <LL_RCC_HSE_EnableBypass>:
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
80012f8: b580 push {r7, lr}
80012fa: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
80012fc: 4b04 ldr r3, [pc, #16] ; (8001310 <LL_RCC_HSE_EnableBypass+0x18>)
80012fe: 681a ldr r2, [r3, #0]
8001300: 4b03 ldr r3, [pc, #12] ; (8001310 <LL_RCC_HSE_EnableBypass+0x18>)
8001302: 2180 movs r1, #128 ; 0x80
8001304: 02c9 lsls r1, r1, #11
8001306: 430a orrs r2, r1
8001308: 601a str r2, [r3, #0]
}
800130a: 46c0 nop ; (mov r8, r8)
800130c: 46bd mov sp, r7
800130e: bd80 pop {r7, pc}
8001310: 40021000 .word 0x40021000
08001314 <LL_RCC_HSE_DisableBypass>:
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
8001314: b580 push {r7, lr}
8001316: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
8001318: 4b04 ldr r3, [pc, #16] ; (800132c <LL_RCC_HSE_DisableBypass+0x18>)
800131a: 681a ldr r2, [r3, #0]
800131c: 4b03 ldr r3, [pc, #12] ; (800132c <LL_RCC_HSE_DisableBypass+0x18>)
800131e: 4904 ldr r1, [pc, #16] ; (8001330 <LL_RCC_HSE_DisableBypass+0x1c>)
8001320: 400a ands r2, r1
8001322: 601a str r2, [r3, #0]
}
8001324: 46c0 nop ; (mov r8, r8)
8001326: 46bd mov sp, r7
8001328: bd80 pop {r7, pc}
800132a: 46c0 nop ; (mov r8, r8)
800132c: 40021000 .word 0x40021000
8001330: fffbffff .word 0xfffbffff
08001334 <LL_RCC_HSE_Enable>:
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
8001334: b580 push {r7, lr}
8001336: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEON);
8001338: 4b04 ldr r3, [pc, #16] ; (800134c <LL_RCC_HSE_Enable+0x18>)
800133a: 681a ldr r2, [r3, #0]
800133c: 4b03 ldr r3, [pc, #12] ; (800134c <LL_RCC_HSE_Enable+0x18>)
800133e: 2180 movs r1, #128 ; 0x80
8001340: 0249 lsls r1, r1, #9
8001342: 430a orrs r2, r1
8001344: 601a str r2, [r3, #0]
}
8001346: 46c0 nop ; (mov r8, r8)
8001348: 46bd mov sp, r7
800134a: bd80 pop {r7, pc}
800134c: 40021000 .word 0x40021000
08001350 <LL_RCC_HSE_IsReady>:
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
8001350: b580 push {r7, lr}
8001352: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
8001354: 4b06 ldr r3, [pc, #24] ; (8001370 <LL_RCC_HSE_IsReady+0x20>)
8001356: 681a ldr r2, [r3, #0]
8001358: 2380 movs r3, #128 ; 0x80
800135a: 029b lsls r3, r3, #10
800135c: 4013 ands r3, r2
800135e: 4a05 ldr r2, [pc, #20] ; (8001374 <LL_RCC_HSE_IsReady+0x24>)
8001360: 4694 mov ip, r2
8001362: 4463 add r3, ip
8001364: 425a negs r2, r3
8001366: 4153 adcs r3, r2
8001368: b2db uxtb r3, r3
}
800136a: 0018 movs r0, r3
800136c: 46bd mov sp, r7
800136e: bd80 pop {r7, pc}
8001370: 40021000 .word 0x40021000
8001374: fffe0000 .word 0xfffe0000
08001378 <LL_RCC_HSI_Enable>:
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
8001378: b580 push {r7, lr}
800137a: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSION);
800137c: 4b04 ldr r3, [pc, #16] ; (8001390 <LL_RCC_HSI_Enable+0x18>)
800137e: 681a ldr r2, [r3, #0]
8001380: 4b03 ldr r3, [pc, #12] ; (8001390 <LL_RCC_HSI_Enable+0x18>)
8001382: 2101 movs r1, #1
8001384: 430a orrs r2, r1
8001386: 601a str r2, [r3, #0]
}
8001388: 46c0 nop ; (mov r8, r8)
800138a: 46bd mov sp, r7
800138c: bd80 pop {r7, pc}
800138e: 46c0 nop ; (mov r8, r8)
8001390: 40021000 .word 0x40021000
08001394 <LL_RCC_HSI_IsReady>:
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
8001394: b580 push {r7, lr}
8001396: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
8001398: 4b05 ldr r3, [pc, #20] ; (80013b0 <LL_RCC_HSI_IsReady+0x1c>)
800139a: 681b ldr r3, [r3, #0]
800139c: 2202 movs r2, #2
800139e: 4013 ands r3, r2
80013a0: 3b02 subs r3, #2
80013a2: 425a negs r2, r3
80013a4: 4153 adcs r3, r2
80013a6: b2db uxtb r3, r3
}
80013a8: 0018 movs r0, r3
80013aa: 46bd mov sp, r7
80013ac: bd80 pop {r7, pc}
80013ae: 46c0 nop ; (mov r8, r8)
80013b0: 40021000 .word 0x40021000
080013b4 <LL_RCC_SetSysClkSource>:
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
80013b4: b580 push {r7, lr}
80013b6: b082 sub sp, #8
80013b8: af00 add r7, sp, #0
80013ba: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
80013bc: 4b06 ldr r3, [pc, #24] ; (80013d8 <LL_RCC_SetSysClkSource+0x24>)
80013be: 685b ldr r3, [r3, #4]
80013c0: 2203 movs r2, #3
80013c2: 4393 bics r3, r2
80013c4: 0019 movs r1, r3
80013c6: 4b04 ldr r3, [pc, #16] ; (80013d8 <LL_RCC_SetSysClkSource+0x24>)
80013c8: 687a ldr r2, [r7, #4]
80013ca: 430a orrs r2, r1
80013cc: 605a str r2, [r3, #4]
}
80013ce: 46c0 nop ; (mov r8, r8)
80013d0: 46bd mov sp, r7
80013d2: b002 add sp, #8
80013d4: bd80 pop {r7, pc}
80013d6: 46c0 nop ; (mov r8, r8)
80013d8: 40021000 .word 0x40021000
080013dc <LL_RCC_GetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
*
* (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
80013dc: b580 push {r7, lr}
80013de: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
80013e0: 4b03 ldr r3, [pc, #12] ; (80013f0 <LL_RCC_GetSysClkSource+0x14>)
80013e2: 685b ldr r3, [r3, #4]
80013e4: 220c movs r2, #12
80013e6: 4013 ands r3, r2
}
80013e8: 0018 movs r0, r3
80013ea: 46bd mov sp, r7
80013ec: bd80 pop {r7, pc}
80013ee: 46c0 nop ; (mov r8, r8)
80013f0: 40021000 .word 0x40021000
080013f4 <LL_RCC_SetAHBPrescaler>:
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
80013f4: b580 push {r7, lr}
80013f6: b082 sub sp, #8
80013f8: af00 add r7, sp, #0
80013fa: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
80013fc: 4b06 ldr r3, [pc, #24] ; (8001418 <LL_RCC_SetAHBPrescaler+0x24>)
80013fe: 685b ldr r3, [r3, #4]
8001400: 22f0 movs r2, #240 ; 0xf0
8001402: 4393 bics r3, r2
8001404: 0019 movs r1, r3
8001406: 4b04 ldr r3, [pc, #16] ; (8001418 <LL_RCC_SetAHBPrescaler+0x24>)
8001408: 687a ldr r2, [r7, #4]
800140a: 430a orrs r2, r1
800140c: 605a str r2, [r3, #4]
}
800140e: 46c0 nop ; (mov r8, r8)
8001410: 46bd mov sp, r7
8001412: b002 add sp, #8
8001414: bd80 pop {r7, pc}
8001416: 46c0 nop ; (mov r8, r8)
8001418: 40021000 .word 0x40021000
0800141c <LL_RCC_SetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
800141c: b580 push {r7, lr}
800141e: b082 sub sp, #8
8001420: af00 add r7, sp, #0
8001422: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
8001424: 4b06 ldr r3, [pc, #24] ; (8001440 <LL_RCC_SetAPB1Prescaler+0x24>)
8001426: 685b ldr r3, [r3, #4]
8001428: 4a06 ldr r2, [pc, #24] ; (8001444 <LL_RCC_SetAPB1Prescaler+0x28>)
800142a: 4013 ands r3, r2
800142c: 0019 movs r1, r3
800142e: 4b04 ldr r3, [pc, #16] ; (8001440 <LL_RCC_SetAPB1Prescaler+0x24>)
8001430: 687a ldr r2, [r7, #4]
8001432: 430a orrs r2, r1
8001434: 605a str r2, [r3, #4]
}
8001436: 46c0 nop ; (mov r8, r8)
8001438: 46bd mov sp, r7
800143a: b002 add sp, #8
800143c: bd80 pop {r7, pc}
800143e: 46c0 nop ; (mov r8, r8)
8001440: 40021000 .word 0x40021000
8001444: fffff8ff .word 0xfffff8ff
08001448 <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
8001448: b580 push {r7, lr}
800144a: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
800144c: 4b04 ldr r3, [pc, #16] ; (8001460 <LL_RCC_PLL_Enable+0x18>)
800144e: 681a ldr r2, [r3, #0]
8001450: 4b03 ldr r3, [pc, #12] ; (8001460 <LL_RCC_PLL_Enable+0x18>)
8001452: 2180 movs r1, #128 ; 0x80
8001454: 0449 lsls r1, r1, #17
8001456: 430a orrs r2, r1
8001458: 601a str r2, [r3, #0]
}
800145a: 46c0 nop ; (mov r8, r8)
800145c: 46bd mov sp, r7
800145e: bd80 pop {r7, pc}
8001460: 40021000 .word 0x40021000
08001464 <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
8001464: b580 push {r7, lr}
8001466: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
8001468: 4b07 ldr r3, [pc, #28] ; (8001488 <LL_RCC_PLL_IsReady+0x24>)
800146a: 681a ldr r2, [r3, #0]
800146c: 2380 movs r3, #128 ; 0x80
800146e: 049b lsls r3, r3, #18
8001470: 4013 ands r3, r2
8001472: 22fe movs r2, #254 ; 0xfe
8001474: 0612 lsls r2, r2, #24
8001476: 4694 mov ip, r2
8001478: 4463 add r3, ip
800147a: 425a negs r2, r3
800147c: 4153 adcs r3, r2
800147e: b2db uxtb r3, r3
}
8001480: 0018 movs r0, r3
8001482: 46bd mov sp, r7
8001484: bd80 pop {r7, pc}
8001486: 46c0 nop ; (mov r8, r8)
8001488: 40021000 .word 0x40021000
0800148c <LL_RCC_PLL_ConfigDomain_SYS>:
* @arg @ref LL_RCC_PLL_MUL_15
* @arg @ref LL_RCC_PLL_MUL_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
{
800148c: b580 push {r7, lr}
800148e: b082 sub sp, #8
8001490: af00 add r7, sp, #0
8001492: 6078 str r0, [r7, #4]
8001494: 6039 str r1, [r7, #0]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
8001496: 4b0e ldr r3, [pc, #56] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
8001498: 685b ldr r3, [r3, #4]
800149a: 4a0e ldr r2, [pc, #56] ; (80014d4 <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
800149c: 4013 ands r3, r2
800149e: 0019 movs r1, r3
80014a0: 687a ldr r2, [r7, #4]
80014a2: 2380 movs r3, #128 ; 0x80
80014a4: 025b lsls r3, r3, #9
80014a6: 401a ands r2, r3
80014a8: 683b ldr r3, [r7, #0]
80014aa: 431a orrs r2, r3
80014ac: 4b08 ldr r3, [pc, #32] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
80014ae: 430a orrs r2, r1
80014b0: 605a str r2, [r3, #4]
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
80014b2: 4b07 ldr r3, [pc, #28] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
80014b4: 6adb ldr r3, [r3, #44] ; 0x2c
80014b6: 220f movs r2, #15
80014b8: 4393 bics r3, r2
80014ba: 0019 movs r1, r3
80014bc: 687b ldr r3, [r7, #4]
80014be: 220f movs r2, #15
80014c0: 401a ands r2, r3
80014c2: 4b03 ldr r3, [pc, #12] ; (80014d0 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
80014c4: 430a orrs r2, r1
80014c6: 62da str r2, [r3, #44] ; 0x2c
}
80014c8: 46c0 nop ; (mov r8, r8)
80014ca: 46bd mov sp, r7
80014cc: b002 add sp, #8
80014ce: bd80 pop {r7, pc}
80014d0: 40021000 .word 0x40021000
80014d4: ffc2ffff .word 0xffc2ffff
080014d8 <LL_InitTick>:
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
80014d8: b580 push {r7, lr}
80014da: b082 sub sp, #8
80014dc: af00 add r7, sp, #0
80014de: 6078 str r0, [r7, #4]
80014e0: 6039 str r1, [r7, #0]
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
80014e2: 6839 ldr r1, [r7, #0]
80014e4: 6878 ldr r0, [r7, #4]
80014e6: f000 fa13 bl 8001910 <__udivsi3>
80014ea: 0003 movs r3, r0
80014ec: 001a movs r2, r3
80014ee: 4b06 ldr r3, [pc, #24] ; (8001508 <LL_InitTick+0x30>)
80014f0: 3a01 subs r2, #1
80014f2: 605a str r2, [r3, #4]
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80014f4: 4b04 ldr r3, [pc, #16] ; (8001508 <LL_InitTick+0x30>)
80014f6: 2200 movs r2, #0
80014f8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80014fa: 4b03 ldr r3, [pc, #12] ; (8001508 <LL_InitTick+0x30>)
80014fc: 2205 movs r2, #5
80014fe: 601a str r2, [r3, #0]
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
8001500: 46c0 nop ; (mov r8, r8)
8001502: 46bd mov sp, r7
8001504: b002 add sp, #8
8001506: bd80 pop {r7, pc}
8001508: e000e010 .word 0xe000e010
0800150c <LL_FLASH_SetLatency>:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
800150c: b580 push {r7, lr}
800150e: b082 sub sp, #8
8001510: af00 add r7, sp, #0
8001512: 6078 str r0, [r7, #4]
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
8001514: 4b06 ldr r3, [pc, #24] ; (8001530 <LL_FLASH_SetLatency+0x24>)
8001516: 681b ldr r3, [r3, #0]
8001518: 2201 movs r2, #1
800151a: 4393 bics r3, r2
800151c: 0019 movs r1, r3
800151e: 4b04 ldr r3, [pc, #16] ; (8001530 <LL_FLASH_SetLatency+0x24>)
8001520: 687a ldr r2, [r7, #4]
8001522: 430a orrs r2, r1
8001524: 601a str r2, [r3, #0]
}
8001526: 46c0 nop ; (mov r8, r8)
8001528: 46bd mov sp, r7
800152a: b002 add sp, #8
800152c: bd80 pop {r7, pc}
800152e: 46c0 nop ; (mov r8, r8)
8001530: 40022000 .word 0x40022000
08001534 <LL_FLASH_GetLatency>:
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
8001534: b580 push {r7, lr}
8001536: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
8001538: 4b03 ldr r3, [pc, #12] ; (8001548 <LL_FLASH_GetLatency+0x14>)
800153a: 681b ldr r3, [r3, #0]
800153c: 2201 movs r2, #1
800153e: 4013 ands r3, r2
}
8001540: 0018 movs r0, r3
8001542: 46bd mov sp, r7
8001544: bd80 pop {r7, pc}
8001546: 46c0 nop ; (mov r8, r8)
8001548: 40022000 .word 0x40022000
0800154c <LL_Init1msTick>:
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
800154c: b580 push {r7, lr}
800154e: b082 sub sp, #8
8001550: af00 add r7, sp, #0
8001552: 6078 str r0, [r7, #4]
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
8001554: 23fa movs r3, #250 ; 0xfa
8001556: 009a lsls r2, r3, #2
8001558: 687b ldr r3, [r7, #4]
800155a: 0011 movs r1, r2
800155c: 0018 movs r0, r3
800155e: f7ff ffbb bl 80014d8 <LL_InitTick>
}
8001562: 46c0 nop ; (mov r8, r8)
8001564: 46bd mov sp, r7
8001566: b002 add sp, #8
8001568: bd80 pop {r7, pc}
0800156a <LL_mDelay>:
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
800156a: b580 push {r7, lr}
800156c: b084 sub sp, #16
800156e: af00 add r7, sp, #0
8001570: 6078 str r0, [r7, #4]
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
8001572: 4b0e ldr r3, [pc, #56] ; (80015ac <LL_mDelay+0x42>)
8001574: 681b ldr r3, [r3, #0]
8001576: 60fb str r3, [r7, #12]
/* Add this code to indicate that local variable is not used */
((void)tmp);
8001578: 68fb ldr r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
800157a: 687b ldr r3, [r7, #4]
800157c: 3301 adds r3, #1
800157e: d00c beq.n 800159a <LL_mDelay+0x30>
{
Delay++;
8001580: 687b ldr r3, [r7, #4]
8001582: 3301 adds r3, #1
8001584: 607b str r3, [r7, #4]
}
while (Delay)
8001586: e008 b.n 800159a <LL_mDelay+0x30>
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
8001588: 4b08 ldr r3, [pc, #32] ; (80015ac <LL_mDelay+0x42>)
800158a: 681a ldr r2, [r3, #0]
800158c: 2380 movs r3, #128 ; 0x80
800158e: 025b lsls r3, r3, #9
8001590: 4013 ands r3, r2
8001592: d002 beq.n 800159a <LL_mDelay+0x30>
{
Delay--;
8001594: 687b ldr r3, [r7, #4]
8001596: 3b01 subs r3, #1
8001598: 607b str r3, [r7, #4]
while (Delay)
800159a: 687b ldr r3, [r7, #4]
800159c: 2b00 cmp r3, #0
800159e: d1f3 bne.n 8001588 <LL_mDelay+0x1e>
}
}
}
80015a0: 46c0 nop ; (mov r8, r8)
80015a2: 46c0 nop ; (mov r8, r8)
80015a4: 46bd mov sp, r7
80015a6: b004 add sp, #16
80015a8: bd80 pop {r7, pc}
80015aa: 46c0 nop ; (mov r8, r8)
80015ac: e000e010 .word 0xe000e010
080015b0 <LL_SetSystemCoreClock>:
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
80015b0: b580 push {r7, lr}
80015b2: b082 sub sp, #8
80015b4: af00 add r7, sp, #0
80015b6: 6078 str r0, [r7, #4]
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
80015b8: 4b03 ldr r3, [pc, #12] ; (80015c8 <LL_SetSystemCoreClock+0x18>)
80015ba: 687a ldr r2, [r7, #4]
80015bc: 601a str r2, [r3, #0]
}
80015be: 46c0 nop ; (mov r8, r8)
80015c0: 46bd mov sp, r7
80015c2: b002 add sp, #8
80015c4: bd80 pop {r7, pc}
80015c6: 46c0 nop ; (mov r8, r8)
80015c8: 20000000 .word 0x20000000
080015cc <LL_PLL_ConfigSystemClock_HSI>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
80015cc: b590 push {r4, r7, lr}
80015ce: b085 sub sp, #20
80015d0: af00 add r7, sp, #0
80015d2: 6078 str r0, [r7, #4]
80015d4: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
80015d6: 230f movs r3, #15
80015d8: 18fb adds r3, r7, r3
80015da: 2201 movs r2, #1
80015dc: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
80015de: 2300 movs r3, #0
80015e0: 60bb str r3, [r7, #8]
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
80015e2: f000 f8d4 bl 800178e <UTILS_PLL_IsBusy>
80015e6: 0003 movs r3, r0
80015e8: 2b01 cmp r3, #1
80015ea: d128 bne.n 800163e <LL_PLL_ConfigSystemClock_HSI+0x72>
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
80015ec: 687b ldr r3, [r7, #4]
80015ee: 2201 movs r2, #1
80015f0: 605a str r2, [r3, #4]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
80015f2: 687b ldr r3, [r7, #4]
80015f4: 4a17 ldr r2, [pc, #92] ; (8001654 <LL_PLL_ConfigSystemClock_HSI+0x88>)
80015f6: 0019 movs r1, r3
80015f8: 0010 movs r0, r2
80015fa: f000 f8ab bl 8001754 <UTILS_GetPLLOutputFrequency>
80015fe: 0003 movs r3, r0
8001600: 60bb str r3, [r7, #8]
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
8001602: f7ff fec7 bl 8001394 <LL_RCC_HSI_IsReady>
8001606: 0003 movs r3, r0
8001608: 2b01 cmp r3, #1
800160a: d007 beq.n 800161c <LL_PLL_ConfigSystemClock_HSI+0x50>
{
LL_RCC_HSI_Enable();
800160c: f7ff feb4 bl 8001378 <LL_RCC_HSI_Enable>
while (LL_RCC_HSI_IsReady() != 1U)
8001610: 46c0 nop ; (mov r8, r8)
8001612: f7ff febf bl 8001394 <LL_RCC_HSI_IsReady>
8001616: 0003 movs r3, r0
8001618: 2b01 cmp r3, #1
800161a: d1fa bne.n 8001612 <LL_PLL_ConfigSystemClock_HSI+0x46>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
800161c: 687b ldr r3, [r7, #4]
800161e: 681b ldr r3, [r3, #0]
8001620: 0019 movs r1, r3
8001622: 2000 movs r0, #0
8001624: f7ff ff32 bl 800148c <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
8001628: 230f movs r3, #15
800162a: 18fc adds r4, r7, r3
800162c: 683a ldr r2, [r7, #0]
800162e: 68bb ldr r3, [r7, #8]
8001630: 0011 movs r1, r2
8001632: 0018 movs r0, r3
8001634: f000 f8be bl 80017b4 <UTILS_EnablePLLAndSwitchSystem>
8001638: 0003 movs r3, r0
800163a: 7023 strb r3, [r4, #0]
800163c: e003 b.n 8001646 <LL_PLL_ConfigSystemClock_HSI+0x7a>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
800163e: 230f movs r3, #15
8001640: 18fb adds r3, r7, r3
8001642: 2200 movs r2, #0
8001644: 701a strb r2, [r3, #0]
}
return status;
8001646: 230f movs r3, #15
8001648: 18fb adds r3, r7, r3
800164a: 781b ldrb r3, [r3, #0]
}
800164c: 0018 movs r0, r3
800164e: 46bd mov sp, r7
8001650: b005 add sp, #20
8001652: bd90 pop {r4, r7, pc}
8001654: 007a1200 .word 0x007a1200
08001658 <LL_PLL_ConfigSystemClock_HSE>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
8001658: b590 push {r4, r7, lr}
800165a: b087 sub sp, #28
800165c: af00 add r7, sp, #0
800165e: 60f8 str r0, [r7, #12]
8001660: 60b9 str r1, [r7, #8]
8001662: 607a str r2, [r7, #4]
8001664: 603b str r3, [r7, #0]
ErrorStatus status = SUCCESS;
8001666: 2317 movs r3, #23
8001668: 18fb adds r3, r7, r3
800166a: 2201 movs r2, #1
800166c: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
800166e: 2300 movs r3, #0
8001670: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
8001672: f000 f88c bl 800178e <UTILS_PLL_IsBusy>
8001676: 0003 movs r3, r0
8001678: 2b01 cmp r3, #1
800167a: d132 bne.n 80016e2 <LL_PLL_ConfigSystemClock_HSE+0x8a>
#else
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
800167c: 687a ldr r2, [r7, #4]
800167e: 68fb ldr r3, [r7, #12]
8001680: 0011 movs r1, r2
8001682: 0018 movs r0, r3
8001684: f000 f866 bl 8001754 <UTILS_GetPLLOutputFrequency>
8001688: 0003 movs r3, r0
800168a: 613b str r3, [r7, #16]
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
800168c: f7ff fe60 bl 8001350 <LL_RCC_HSE_IsReady>
8001690: 0003 movs r3, r0
8001692: 2b01 cmp r3, #1
8001694: d00f beq.n 80016b6 <LL_PLL_ConfigSystemClock_HSE+0x5e>
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
8001696: 68bb ldr r3, [r7, #8]
8001698: 2b01 cmp r3, #1
800169a: d102 bne.n 80016a2 <LL_PLL_ConfigSystemClock_HSE+0x4a>
{
LL_RCC_HSE_EnableBypass();
800169c: f7ff fe2c bl 80012f8 <LL_RCC_HSE_EnableBypass>
80016a0: e001 b.n 80016a6 <LL_PLL_ConfigSystemClock_HSE+0x4e>
}
else
{
LL_RCC_HSE_DisableBypass();
80016a2: f7ff fe37 bl 8001314 <LL_RCC_HSE_DisableBypass>
}
/* Enable HSE */
LL_RCC_HSE_Enable();
80016a6: f7ff fe45 bl 8001334 <LL_RCC_HSE_Enable>
while (LL_RCC_HSE_IsReady() != 1U)
80016aa: 46c0 nop ; (mov r8, r8)
80016ac: f7ff fe50 bl 8001350 <LL_RCC_HSE_IsReady>
80016b0: 0003 movs r3, r0
80016b2: 2b01 cmp r3, #1
80016b4: d1fa bne.n 80016ac <LL_PLL_ConfigSystemClock_HSE+0x54>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
80016b6: 687b ldr r3, [r7, #4]
80016b8: 685b ldr r3, [r3, #4]
80016ba: 2280 movs r2, #128 ; 0x80
80016bc: 0252 lsls r2, r2, #9
80016be: 431a orrs r2, r3
80016c0: 687b ldr r3, [r7, #4]
80016c2: 681b ldr r3, [r3, #0]
80016c4: 0019 movs r1, r3
80016c6: 0010 movs r0, r2
80016c8: f7ff fee0 bl 800148c <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
80016cc: 2317 movs r3, #23
80016ce: 18fc adds r4, r7, r3
80016d0: 683a ldr r2, [r7, #0]
80016d2: 693b ldr r3, [r7, #16]
80016d4: 0011 movs r1, r2
80016d6: 0018 movs r0, r3
80016d8: f000 f86c bl 80017b4 <UTILS_EnablePLLAndSwitchSystem>
80016dc: 0003 movs r3, r0
80016de: 7023 strb r3, [r4, #0]
80016e0: e003 b.n 80016ea <LL_PLL_ConfigSystemClock_HSE+0x92>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
80016e2: 2317 movs r3, #23
80016e4: 18fb adds r3, r7, r3
80016e6: 2200 movs r2, #0
80016e8: 701a strb r2, [r3, #0]
}
return status;
80016ea: 2317 movs r3, #23
80016ec: 18fb adds r3, r7, r3
80016ee: 781b ldrb r3, [r3, #0]
}
80016f0: 0018 movs r0, r3
80016f2: 46bd mov sp, r7
80016f4: b007 add sp, #28
80016f6: bd90 pop {r4, r7, pc}
080016f8 <UTILS_SetFlashLatency>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
80016f8: b580 push {r7, lr}
80016fa: b084 sub sp, #16
80016fc: af00 add r7, sp, #0
80016fe: 6078 str r0, [r7, #4]
ErrorStatus status = SUCCESS;
8001700: 210f movs r1, #15
8001702: 187b adds r3, r7, r1
8001704: 2201 movs r2, #1
8001706: 701a strb r2, [r3, #0]
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
8001708: 2300 movs r3, #0
800170a: 60bb str r3, [r7, #8]
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
800170c: 687b ldr r3, [r7, #4]
800170e: 2b00 cmp r3, #0
8001710: d103 bne.n 800171a <UTILS_SetFlashLatency+0x22>
{
status = ERROR;
8001712: 187b adds r3, r7, r1
8001714: 2200 movs r2, #0
8001716: 701a strb r2, [r3, #0]
8001718: e013 b.n 8001742 <UTILS_SetFlashLatency+0x4a>
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
800171a: 687b ldr r3, [r7, #4]
800171c: 4a0c ldr r2, [pc, #48] ; (8001750 <UTILS_SetFlashLatency+0x58>)
800171e: 4293 cmp r3, r2
8001720: d901 bls.n 8001726 <UTILS_SetFlashLatency+0x2e>
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
8001722: 2301 movs r3, #1
8001724: 60bb str r3, [r7, #8]
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
LL_FLASH_SetLatency(latency);
8001726: 68bb ldr r3, [r7, #8]
8001728: 0018 movs r0, r3
800172a: f7ff feef bl 800150c <LL_FLASH_SetLatency>
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
800172e: f7ff ff01 bl 8001534 <LL_FLASH_GetLatency>
8001732: 0002 movs r2, r0
8001734: 68bb ldr r3, [r7, #8]
8001736: 4293 cmp r3, r2
8001738: d003 beq.n 8001742 <UTILS_SetFlashLatency+0x4a>
{
status = ERROR;
800173a: 230f movs r3, #15
800173c: 18fb adds r3, r7, r3
800173e: 2200 movs r2, #0
8001740: 701a strb r2, [r3, #0]
}
}
return status;
8001742: 230f movs r3, #15
8001744: 18fb adds r3, r7, r3
8001746: 781b ldrb r3, [r3, #0]
}
8001748: 0018 movs r0, r3
800174a: 46bd mov sp, r7
800174c: b004 add sp, #16
800174e: bd80 pop {r7, pc}
8001750: 016e3600 .word 0x016e3600
08001754 <UTILS_GetPLLOutputFrequency>:
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
8001754: b580 push {r7, lr}
8001756: b084 sub sp, #16
8001758: af00 add r7, sp, #0
800175a: 6078 str r0, [r7, #4]
800175c: 6039 str r1, [r7, #0]
uint32_t pllfreq = 0U;
800175e: 2300 movs r3, #0
8001760: 60fb str r3, [r7, #12]
/* The application software must set correctly the PLL multiplication factor to
be in the range 16-48MHz */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
8001762: 683b ldr r3, [r7, #0]
8001764: 685b ldr r3, [r3, #4]
8001766: 3301 adds r3, #1
8001768: 0019 movs r1, r3
800176a: 6878 ldr r0, [r7, #4]
800176c: f000 f8d0 bl 8001910 <__udivsi3>
8001770: 0003 movs r3, r0
8001772: 0019 movs r1, r3
8001774: 683b ldr r3, [r7, #0]
8001776: 681b ldr r3, [r3, #0]
8001778: 0c9b lsrs r3, r3, #18
800177a: 220f movs r2, #15
800177c: 4013 ands r3, r2
800177e: 3302 adds r3, #2
8001780: 434b muls r3, r1
8001782: 60fb str r3, [r7, #12]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
8001784: 68fb ldr r3, [r7, #12]
}
8001786: 0018 movs r0, r3
8001788: 46bd mov sp, r7
800178a: b004 add sp, #16
800178c: bd80 pop {r7, pc}
0800178e <UTILS_PLL_IsBusy>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
800178e: b580 push {r7, lr}
8001790: b082 sub sp, #8
8001792: af00 add r7, sp, #0
ErrorStatus status = SUCCESS;
8001794: 1dfb adds r3, r7, #7
8001796: 2201 movs r2, #1
8001798: 701a strb r2, [r3, #0]
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
800179a: f7ff fe63 bl 8001464 <LL_RCC_PLL_IsReady>
800179e: 1e03 subs r3, r0, #0
80017a0: d002 beq.n 80017a8 <UTILS_PLL_IsBusy+0x1a>
{
/* PLL configuration cannot be modified */
status = ERROR;
80017a2: 1dfb adds r3, r7, #7
80017a4: 2200 movs r2, #0
80017a6: 701a strb r2, [r3, #0]
}
return status;
80017a8: 1dfb adds r3, r7, #7
80017aa: 781b ldrb r3, [r3, #0]
}
80017ac: 0018 movs r0, r3
80017ae: 46bd mov sp, r7
80017b0: b002 add sp, #8
80017b2: bd80 pop {r7, pc}
080017b4 <UTILS_EnablePLLAndSwitchSystem>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
80017b4: b590 push {r4, r7, lr}
80017b6: b085 sub sp, #20
80017b8: af00 add r7, sp, #0
80017ba: 6078 str r0, [r7, #4]
80017bc: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
80017be: 200f movs r0, #15
80017c0: 183b adds r3, r7, r0
80017c2: 2201 movs r2, #1
80017c4: 701a strb r2, [r3, #0]
uint32_t sysclk_frequency_current = 0U;
80017c6: 2300 movs r3, #0
80017c8: 60bb str r3, [r7, #8]
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
80017ca: 4b2e ldr r3, [pc, #184] ; (8001884 <UTILS_EnablePLLAndSwitchSystem+0xd0>)
80017cc: 681a ldr r2, [r3, #0]
80017ce: 683b ldr r3, [r7, #0]
80017d0: 681b ldr r3, [r3, #0]
80017d2: 091b lsrs r3, r3, #4
80017d4: 210f movs r1, #15
80017d6: 400b ands r3, r1
80017d8: 492b ldr r1, [pc, #172] ; (8001888 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
80017da: 5ccb ldrb r3, [r1, r3]
80017dc: 409a lsls r2, r3
80017de: 0013 movs r3, r2
80017e0: 60bb str r3, [r7, #8]
/* Increasing the number of wait states because of higher CPU frequency */
if (sysclk_frequency_current < SYSCLK_Frequency)
80017e2: 68ba ldr r2, [r7, #8]
80017e4: 687b ldr r3, [r7, #4]
80017e6: 429a cmp r2, r3
80017e8: d206 bcs.n 80017f8 <UTILS_EnablePLLAndSwitchSystem+0x44>
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
80017ea: 183c adds r4, r7, r0
80017ec: 687b ldr r3, [r7, #4]
80017ee: 0018 movs r0, r3
80017f0: f7ff ff82 bl 80016f8 <UTILS_SetFlashLatency>
80017f4: 0003 movs r3, r0
80017f6: 7023 strb r3, [r4, #0]
}
/* Update system clock configuration */
if (status == SUCCESS)
80017f8: 230f movs r3, #15
80017fa: 18fb adds r3, r7, r3
80017fc: 781b ldrb r3, [r3, #0]
80017fe: 2b01 cmp r3, #1
8001800: d11a bne.n 8001838 <UTILS_EnablePLLAndSwitchSystem+0x84>
{
/* Enable PLL */
LL_RCC_PLL_Enable();
8001802: f7ff fe21 bl 8001448 <LL_RCC_PLL_Enable>
while (LL_RCC_PLL_IsReady() != 1U)
8001806: 46c0 nop ; (mov r8, r8)
8001808: f7ff fe2c bl 8001464 <LL_RCC_PLL_IsReady>
800180c: 0003 movs r3, r0
800180e: 2b01 cmp r3, #1
8001810: d1fa bne.n 8001808 <UTILS_EnablePLLAndSwitchSystem+0x54>
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
8001812: 683b ldr r3, [r7, #0]
8001814: 681b ldr r3, [r3, #0]
8001816: 0018 movs r0, r3
8001818: f7ff fdec bl 80013f4 <LL_RCC_SetAHBPrescaler>
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
800181c: 2002 movs r0, #2
800181e: f7ff fdc9 bl 80013b4 <LL_RCC_SetSysClkSource>
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
8001822: 46c0 nop ; (mov r8, r8)
8001824: f7ff fdda bl 80013dc <LL_RCC_GetSysClkSource>
8001828: 0003 movs r3, r0
800182a: 2b08 cmp r3, #8
800182c: d1fa bne.n 8001824 <UTILS_EnablePLLAndSwitchSystem+0x70>
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
800182e: 683b ldr r3, [r7, #0]
8001830: 685b ldr r3, [r3, #4]
8001832: 0018 movs r0, r3
8001834: f7ff fdf2 bl 800141c <LL_RCC_SetAPB1Prescaler>
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (sysclk_frequency_current > SYSCLK_Frequency)
8001838: 68ba ldr r2, [r7, #8]
800183a: 687b ldr r3, [r7, #4]
800183c: 429a cmp r2, r3
800183e: d907 bls.n 8001850 <UTILS_EnablePLLAndSwitchSystem+0x9c>
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
8001840: 230f movs r3, #15
8001842: 18fc adds r4, r7, r3
8001844: 687b ldr r3, [r7, #4]
8001846: 0018 movs r0, r3
8001848: f7ff ff56 bl 80016f8 <UTILS_SetFlashLatency>
800184c: 0003 movs r3, r0
800184e: 7023 strb r3, [r4, #0]
}
/* Update SystemCoreClock variable */
if (status == SUCCESS)
8001850: 230f movs r3, #15
8001852: 18fb adds r3, r7, r3
8001854: 781b ldrb r3, [r3, #0]
8001856: 2b01 cmp r3, #1
8001858: d10c bne.n 8001874 <UTILS_EnablePLLAndSwitchSystem+0xc0>
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
800185a: 683b ldr r3, [r7, #0]
800185c: 681b ldr r3, [r3, #0]
800185e: 091b lsrs r3, r3, #4
8001860: 220f movs r2, #15
8001862: 4013 ands r3, r2
8001864: 4a08 ldr r2, [pc, #32] ; (8001888 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
8001866: 5cd3 ldrb r3, [r2, r3]
8001868: 001a movs r2, r3
800186a: 687b ldr r3, [r7, #4]
800186c: 40d3 lsrs r3, r2
800186e: 0018 movs r0, r3
8001870: f7ff fe9e bl 80015b0 <LL_SetSystemCoreClock>
}
return status;
8001874: 230f movs r3, #15
8001876: 18fb adds r3, r7, r3
8001878: 781b ldrb r3, [r3, #0]
}
800187a: 0018 movs r0, r3
800187c: 46bd mov sp, r7
800187e: b005 add sp, #20
8001880: bd90 pop {r4, r7, pc}
8001882: 46c0 nop ; (mov r8, r8)
8001884: 20000000 .word 0x20000000
8001888: 08001c4c .word 0x08001c4c
0800188c <__sinit>:
#include <stdbool.h>
int __errno = 0;
void *_impure_ptr = NULL;
void __sinit(void) {
800188c: b580 push {r7, lr}
800188e: af00 add r7, sp, #0
}
8001890: 46c0 nop ; (mov r8, r8)
8001892: 46bd mov sp, r7
8001894: bd80 pop {r7, pc}
08001896 <memset>:
void *memset(void *s, int c, size_t n) {
8001896: b580 push {r7, lr}
8001898: b086 sub sp, #24
800189a: af00 add r7, sp, #0
800189c: 60f8 str r0, [r7, #12]
800189e: 60b9 str r1, [r7, #8]
80018a0: 607a str r2, [r7, #4]
char *end = (char *)s + n;
80018a2: 68fa ldr r2, [r7, #12]
80018a4: 687b ldr r3, [r7, #4]
80018a6: 18d3 adds r3, r2, r3
80018a8: 613b str r3, [r7, #16]
for (char *p = (char *)s; p < end; p++)
80018aa: 68fb ldr r3, [r7, #12]
80018ac: 617b str r3, [r7, #20]
80018ae: e006 b.n 80018be <memset+0x28>
*p = (char)c;
80018b0: 68bb ldr r3, [r7, #8]
80018b2: b2da uxtb r2, r3
80018b4: 697b ldr r3, [r7, #20]
80018b6: 701a strb r2, [r3, #0]
for (char *p = (char *)s; p < end; p++)
80018b8: 697b ldr r3, [r7, #20]
80018ba: 3301 adds r3, #1
80018bc: 617b str r3, [r7, #20]
80018be: 697a ldr r2, [r7, #20]
80018c0: 693b ldr r3, [r7, #16]
80018c2: 429a cmp r2, r3
80018c4: d3f4 bcc.n 80018b0 <memset+0x1a>
return s;
80018c6: 68fb ldr r3, [r7, #12]
}
80018c8: 0018 movs r0, r3
80018ca: 46bd mov sp, r7
80018cc: b006 add sp, #24
80018ce: bd80 pop {r7, pc}
080018d0 <strlen>:
size_t strlen(const char *s) {
80018d0: b580 push {r7, lr}
80018d2: b084 sub sp, #16
80018d4: af00 add r7, sp, #0
80018d6: 6078 str r0, [r7, #4]
const char *start = s;
80018d8: 687b ldr r3, [r7, #4]
80018da: 60fb str r3, [r7, #12]
while (*s++);
80018dc: 46c0 nop ; (mov r8, r8)
80018de: 687b ldr r3, [r7, #4]
80018e0: 1c5a adds r2, r3, #1
80018e2: 607a str r2, [r7, #4]
80018e4: 781b ldrb r3, [r3, #0]
80018e6: 2b00 cmp r3, #0
80018e8: d1f9 bne.n 80018de <strlen+0xe>
return s - start - 1;
80018ea: 687a ldr r2, [r7, #4]
80018ec: 68fb ldr r3, [r7, #12]
80018ee: 1ad3 subs r3, r2, r3
80018f0: 3b01 subs r3, #1
}
80018f2: 0018 movs r0, r3
80018f4: 46bd mov sp, r7
80018f6: b004 add sp, #16
80018f8: bd80 pop {r7, pc}
080018fa <__assert_func>:
void __assert_func(bool value) {
80018fa: b580 push {r7, lr}
80018fc: b082 sub sp, #8
80018fe: af00 add r7, sp, #0
8001900: 0002 movs r2, r0
8001902: 1dfb adds r3, r7, #7
8001904: 701a strb r2, [r3, #0]
}
8001906: 46c0 nop ; (mov r8, r8)
8001908: 46bd mov sp, r7
800190a: b002 add sp, #8
800190c: bd80 pop {r7, pc}
...
08001910 <__udivsi3>:
8001910: 2200 movs r2, #0
8001912: 0843 lsrs r3, r0, #1
8001914: 428b cmp r3, r1
8001916: d374 bcc.n 8001a02 <__udivsi3+0xf2>
8001918: 0903 lsrs r3, r0, #4
800191a: 428b cmp r3, r1
800191c: d35f bcc.n 80019de <__udivsi3+0xce>
800191e: 0a03 lsrs r3, r0, #8
8001920: 428b cmp r3, r1
8001922: d344 bcc.n 80019ae <__udivsi3+0x9e>
8001924: 0b03 lsrs r3, r0, #12
8001926: 428b cmp r3, r1
8001928: d328 bcc.n 800197c <__udivsi3+0x6c>
800192a: 0c03 lsrs r3, r0, #16
800192c: 428b cmp r3, r1
800192e: d30d bcc.n 800194c <__udivsi3+0x3c>
8001930: 22ff movs r2, #255 ; 0xff
8001932: 0209 lsls r1, r1, #8
8001934: ba12 rev r2, r2
8001936: 0c03 lsrs r3, r0, #16
8001938: 428b cmp r3, r1
800193a: d302 bcc.n 8001942 <__udivsi3+0x32>
800193c: 1212 asrs r2, r2, #8
800193e: 0209 lsls r1, r1, #8
8001940: d065 beq.n 8001a0e <__udivsi3+0xfe>
8001942: 0b03 lsrs r3, r0, #12
8001944: 428b cmp r3, r1
8001946: d319 bcc.n 800197c <__udivsi3+0x6c>
8001948: e000 b.n 800194c <__udivsi3+0x3c>
800194a: 0a09 lsrs r1, r1, #8
800194c: 0bc3 lsrs r3, r0, #15
800194e: 428b cmp r3, r1
8001950: d301 bcc.n 8001956 <__udivsi3+0x46>
8001952: 03cb lsls r3, r1, #15
8001954: 1ac0 subs r0, r0, r3
8001956: 4152 adcs r2, r2
8001958: 0b83 lsrs r3, r0, #14
800195a: 428b cmp r3, r1
800195c: d301 bcc.n 8001962 <__udivsi3+0x52>
800195e: 038b lsls r3, r1, #14
8001960: 1ac0 subs r0, r0, r3
8001962: 4152 adcs r2, r2
8001964: 0b43 lsrs r3, r0, #13
8001966: 428b cmp r3, r1
8001968: d301 bcc.n 800196e <__udivsi3+0x5e>
800196a: 034b lsls r3, r1, #13
800196c: 1ac0 subs r0, r0, r3
800196e: 4152 adcs r2, r2
8001970: 0b03 lsrs r3, r0, #12
8001972: 428b cmp r3, r1
8001974: d301 bcc.n 800197a <__udivsi3+0x6a>
8001976: 030b lsls r3, r1, #12
8001978: 1ac0 subs r0, r0, r3
800197a: 4152 adcs r2, r2
800197c: 0ac3 lsrs r3, r0, #11
800197e: 428b cmp r3, r1
8001980: d301 bcc.n 8001986 <__udivsi3+0x76>
8001982: 02cb lsls r3, r1, #11
8001984: 1ac0 subs r0, r0, r3
8001986: 4152 adcs r2, r2
8001988: 0a83 lsrs r3, r0, #10
800198a: 428b cmp r3, r1
800198c: d301 bcc.n 8001992 <__udivsi3+0x82>
800198e: 028b lsls r3, r1, #10
8001990: 1ac0 subs r0, r0, r3
8001992: 4152 adcs r2, r2
8001994: 0a43 lsrs r3, r0, #9
8001996: 428b cmp r3, r1
8001998: d301 bcc.n 800199e <__udivsi3+0x8e>
800199a: 024b lsls r3, r1, #9
800199c: 1ac0 subs r0, r0, r3
800199e: 4152 adcs r2, r2
80019a0: 0a03 lsrs r3, r0, #8
80019a2: 428b cmp r3, r1
80019a4: d301 bcc.n 80019aa <__udivsi3+0x9a>
80019a6: 020b lsls r3, r1, #8
80019a8: 1ac0 subs r0, r0, r3
80019aa: 4152 adcs r2, r2
80019ac: d2cd bcs.n 800194a <__udivsi3+0x3a>
80019ae: 09c3 lsrs r3, r0, #7
80019b0: 428b cmp r3, r1
80019b2: d301 bcc.n 80019b8 <__udivsi3+0xa8>
80019b4: 01cb lsls r3, r1, #7
80019b6: 1ac0 subs r0, r0, r3
80019b8: 4152 adcs r2, r2
80019ba: 0983 lsrs r3, r0, #6
80019bc: 428b cmp r3, r1
80019be: d301 bcc.n 80019c4 <__udivsi3+0xb4>
80019c0: 018b lsls r3, r1, #6
80019c2: 1ac0 subs r0, r0, r3
80019c4: 4152 adcs r2, r2
80019c6: 0943 lsrs r3, r0, #5
80019c8: 428b cmp r3, r1
80019ca: d301 bcc.n 80019d0 <__udivsi3+0xc0>
80019cc: 014b lsls r3, r1, #5
80019ce: 1ac0 subs r0, r0, r3
80019d0: 4152 adcs r2, r2
80019d2: 0903 lsrs r3, r0, #4
80019d4: 428b cmp r3, r1
80019d6: d301 bcc.n 80019dc <__udivsi3+0xcc>
80019d8: 010b lsls r3, r1, #4
80019da: 1ac0 subs r0, r0, r3
80019dc: 4152 adcs r2, r2
80019de: 08c3 lsrs r3, r0, #3
80019e0: 428b cmp r3, r1
80019e2: d301 bcc.n 80019e8 <__udivsi3+0xd8>
80019e4: 00cb lsls r3, r1, #3
80019e6: 1ac0 subs r0, r0, r3
80019e8: 4152 adcs r2, r2
80019ea: 0883 lsrs r3, r0, #2
80019ec: 428b cmp r3, r1
80019ee: d301 bcc.n 80019f4 <__udivsi3+0xe4>
80019f0: 008b lsls r3, r1, #2
80019f2: 1ac0 subs r0, r0, r3
80019f4: 4152 adcs r2, r2
80019f6: 0843 lsrs r3, r0, #1
80019f8: 428b cmp r3, r1
80019fa: d301 bcc.n 8001a00 <__udivsi3+0xf0>
80019fc: 004b lsls r3, r1, #1
80019fe: 1ac0 subs r0, r0, r3
8001a00: 4152 adcs r2, r2
8001a02: 1a41 subs r1, r0, r1
8001a04: d200 bcs.n 8001a08 <__udivsi3+0xf8>
8001a06: 4601 mov r1, r0
8001a08: 4152 adcs r2, r2
8001a0a: 4610 mov r0, r2
8001a0c: 4770 bx lr
8001a0e: e7ff b.n 8001a10 <__udivsi3+0x100>
8001a10: b501 push {r0, lr}
8001a12: 2000 movs r0, #0
8001a14: f000 f8f0 bl 8001bf8 <__aeabi_idiv0>
8001a18: bd02 pop {r1, pc}
8001a1a: 46c0 nop ; (mov r8, r8)
08001a1c <__aeabi_uidivmod>:
8001a1c: 2900 cmp r1, #0
8001a1e: d0f7 beq.n 8001a10 <__udivsi3+0x100>
8001a20: e776 b.n 8001910 <__udivsi3>
8001a22: 4770 bx lr
08001a24 <__divsi3>:
8001a24: 4603 mov r3, r0
8001a26: 430b orrs r3, r1
8001a28: d47f bmi.n 8001b2a <__divsi3+0x106>
8001a2a: 2200 movs r2, #0
8001a2c: 0843 lsrs r3, r0, #1
8001a2e: 428b cmp r3, r1
8001a30: d374 bcc.n 8001b1c <__divsi3+0xf8>
8001a32: 0903 lsrs r3, r0, #4
8001a34: 428b cmp r3, r1
8001a36: d35f bcc.n 8001af8 <__divsi3+0xd4>
8001a38: 0a03 lsrs r3, r0, #8
8001a3a: 428b cmp r3, r1
8001a3c: d344 bcc.n 8001ac8 <__divsi3+0xa4>
8001a3e: 0b03 lsrs r3, r0, #12
8001a40: 428b cmp r3, r1
8001a42: d328 bcc.n 8001a96 <__divsi3+0x72>
8001a44: 0c03 lsrs r3, r0, #16
8001a46: 428b cmp r3, r1
8001a48: d30d bcc.n 8001a66 <__divsi3+0x42>
8001a4a: 22ff movs r2, #255 ; 0xff
8001a4c: 0209 lsls r1, r1, #8
8001a4e: ba12 rev r2, r2
8001a50: 0c03 lsrs r3, r0, #16
8001a52: 428b cmp r3, r1
8001a54: d302 bcc.n 8001a5c <__divsi3+0x38>
8001a56: 1212 asrs r2, r2, #8
8001a58: 0209 lsls r1, r1, #8
8001a5a: d065 beq.n 8001b28 <__divsi3+0x104>
8001a5c: 0b03 lsrs r3, r0, #12
8001a5e: 428b cmp r3, r1
8001a60: d319 bcc.n 8001a96 <__divsi3+0x72>
8001a62: e000 b.n 8001a66 <__divsi3+0x42>
8001a64: 0a09 lsrs r1, r1, #8
8001a66: 0bc3 lsrs r3, r0, #15
8001a68: 428b cmp r3, r1
8001a6a: d301 bcc.n 8001a70 <__divsi3+0x4c>
8001a6c: 03cb lsls r3, r1, #15
8001a6e: 1ac0 subs r0, r0, r3
8001a70: 4152 adcs r2, r2
8001a72: 0b83 lsrs r3, r0, #14
8001a74: 428b cmp r3, r1
8001a76: d301 bcc.n 8001a7c <__divsi3+0x58>
8001a78: 038b lsls r3, r1, #14
8001a7a: 1ac0 subs r0, r0, r3
8001a7c: 4152 adcs r2, r2
8001a7e: 0b43 lsrs r3, r0, #13
8001a80: 428b cmp r3, r1
8001a82: d301 bcc.n 8001a88 <__divsi3+0x64>
8001a84: 034b lsls r3, r1, #13
8001a86: 1ac0 subs r0, r0, r3
8001a88: 4152 adcs r2, r2
8001a8a: 0b03 lsrs r3, r0, #12
8001a8c: 428b cmp r3, r1
8001a8e: d301 bcc.n 8001a94 <__divsi3+0x70>
8001a90: 030b lsls r3, r1, #12
8001a92: 1ac0 subs r0, r0, r3
8001a94: 4152 adcs r2, r2
8001a96: 0ac3 lsrs r3, r0, #11
8001a98: 428b cmp r3, r1
8001a9a: d301 bcc.n 8001aa0 <__divsi3+0x7c>
8001a9c: 02cb lsls r3, r1, #11
8001a9e: 1ac0 subs r0, r0, r3
8001aa0: 4152 adcs r2, r2
8001aa2: 0a83 lsrs r3, r0, #10
8001aa4: 428b cmp r3, r1
8001aa6: d301 bcc.n 8001aac <__divsi3+0x88>
8001aa8: 028b lsls r3, r1, #10
8001aaa: 1ac0 subs r0, r0, r3
8001aac: 4152 adcs r2, r2
8001aae: 0a43 lsrs r3, r0, #9
8001ab0: 428b cmp r3, r1
8001ab2: d301 bcc.n 8001ab8 <__divsi3+0x94>
8001ab4: 024b lsls r3, r1, #9
8001ab6: 1ac0 subs r0, r0, r3
8001ab8: 4152 adcs r2, r2
8001aba: 0a03 lsrs r3, r0, #8
8001abc: 428b cmp r3, r1
8001abe: d301 bcc.n 8001ac4 <__divsi3+0xa0>
8001ac0: 020b lsls r3, r1, #8
8001ac2: 1ac0 subs r0, r0, r3
8001ac4: 4152 adcs r2, r2
8001ac6: d2cd bcs.n 8001a64 <__divsi3+0x40>
8001ac8: 09c3 lsrs r3, r0, #7
8001aca: 428b cmp r3, r1
8001acc: d301 bcc.n 8001ad2 <__divsi3+0xae>
8001ace: 01cb lsls r3, r1, #7
8001ad0: 1ac0 subs r0, r0, r3
8001ad2: 4152 adcs r2, r2
8001ad4: 0983 lsrs r3, r0, #6
8001ad6: 428b cmp r3, r1
8001ad8: d301 bcc.n 8001ade <__divsi3+0xba>
8001ada: 018b lsls r3, r1, #6
8001adc: 1ac0 subs r0, r0, r3
8001ade: 4152 adcs r2, r2
8001ae0: 0943 lsrs r3, r0, #5
8001ae2: 428b cmp r3, r1
8001ae4: d301 bcc.n 8001aea <__divsi3+0xc6>
8001ae6: 014b lsls r3, r1, #5
8001ae8: 1ac0 subs r0, r0, r3
8001aea: 4152 adcs r2, r2
8001aec: 0903 lsrs r3, r0, #4
8001aee: 428b cmp r3, r1
8001af0: d301 bcc.n 8001af6 <__divsi3+0xd2>
8001af2: 010b lsls r3, r1, #4
8001af4: 1ac0 subs r0, r0, r3
8001af6: 4152 adcs r2, r2
8001af8: 08c3 lsrs r3, r0, #3
8001afa: 428b cmp r3, r1
8001afc: d301 bcc.n 8001b02 <__divsi3+0xde>
8001afe: 00cb lsls r3, r1, #3
8001b00: 1ac0 subs r0, r0, r3
8001b02: 4152 adcs r2, r2
8001b04: 0883 lsrs r3, r0, #2
8001b06: 428b cmp r3, r1
8001b08: d301 bcc.n 8001b0e <__divsi3+0xea>
8001b0a: 008b lsls r3, r1, #2
8001b0c: 1ac0 subs r0, r0, r3
8001b0e: 4152 adcs r2, r2
8001b10: 0843 lsrs r3, r0, #1
8001b12: 428b cmp r3, r1
8001b14: d301 bcc.n 8001b1a <__divsi3+0xf6>
8001b16: 004b lsls r3, r1, #1
8001b18: 1ac0 subs r0, r0, r3
8001b1a: 4152 adcs r2, r2
8001b1c: 1a41 subs r1, r0, r1
8001b1e: d200 bcs.n 8001b22 <__divsi3+0xfe>
8001b20: 4601 mov r1, r0
8001b22: 4152 adcs r2, r2
8001b24: 4610 mov r0, r2
8001b26: 4770 bx lr
8001b28: e05d b.n 8001be6 <__divsi3+0x1c2>
8001b2a: 0fca lsrs r2, r1, #31
8001b2c: d000 beq.n 8001b30 <__divsi3+0x10c>
8001b2e: 4249 negs r1, r1
8001b30: 1003 asrs r3, r0, #32
8001b32: d300 bcc.n 8001b36 <__divsi3+0x112>
8001b34: 4240 negs r0, r0
8001b36: 4053 eors r3, r2
8001b38: 2200 movs r2, #0
8001b3a: 469c mov ip, r3
8001b3c: 0903 lsrs r3, r0, #4
8001b3e: 428b cmp r3, r1
8001b40: d32d bcc.n 8001b9e <__divsi3+0x17a>
8001b42: 0a03 lsrs r3, r0, #8
8001b44: 428b cmp r3, r1
8001b46: d312 bcc.n 8001b6e <__divsi3+0x14a>
8001b48: 22fc movs r2, #252 ; 0xfc
8001b4a: 0189 lsls r1, r1, #6
8001b4c: ba12 rev r2, r2
8001b4e: 0a03 lsrs r3, r0, #8
8001b50: 428b cmp r3, r1
8001b52: d30c bcc.n 8001b6e <__divsi3+0x14a>
8001b54: 0189 lsls r1, r1, #6
8001b56: 1192 asrs r2, r2, #6
8001b58: 428b cmp r3, r1
8001b5a: d308 bcc.n 8001b6e <__divsi3+0x14a>
8001b5c: 0189 lsls r1, r1, #6
8001b5e: 1192 asrs r2, r2, #6
8001b60: 428b cmp r3, r1
8001b62: d304 bcc.n 8001b6e <__divsi3+0x14a>
8001b64: 0189 lsls r1, r1, #6
8001b66: d03a beq.n 8001bde <__divsi3+0x1ba>
8001b68: 1192 asrs r2, r2, #6
8001b6a: e000 b.n 8001b6e <__divsi3+0x14a>
8001b6c: 0989 lsrs r1, r1, #6
8001b6e: 09c3 lsrs r3, r0, #7
8001b70: 428b cmp r3, r1
8001b72: d301 bcc.n 8001b78 <__divsi3+0x154>
8001b74: 01cb lsls r3, r1, #7
8001b76: 1ac0 subs r0, r0, r3
8001b78: 4152 adcs r2, r2
8001b7a: 0983 lsrs r3, r0, #6
8001b7c: 428b cmp r3, r1
8001b7e: d301 bcc.n 8001b84 <__divsi3+0x160>
8001b80: 018b lsls r3, r1, #6
8001b82: 1ac0 subs r0, r0, r3
8001b84: 4152 adcs r2, r2
8001b86: 0943 lsrs r3, r0, #5
8001b88: 428b cmp r3, r1
8001b8a: d301 bcc.n 8001b90 <__divsi3+0x16c>
8001b8c: 014b lsls r3, r1, #5
8001b8e: 1ac0 subs r0, r0, r3
8001b90: 4152 adcs r2, r2
8001b92: 0903 lsrs r3, r0, #4
8001b94: 428b cmp r3, r1
8001b96: d301 bcc.n 8001b9c <__divsi3+0x178>
8001b98: 010b lsls r3, r1, #4
8001b9a: 1ac0 subs r0, r0, r3
8001b9c: 4152 adcs r2, r2
8001b9e: 08c3 lsrs r3, r0, #3
8001ba0: 428b cmp r3, r1
8001ba2: d301 bcc.n 8001ba8 <__divsi3+0x184>
8001ba4: 00cb lsls r3, r1, #3
8001ba6: 1ac0 subs r0, r0, r3
8001ba8: 4152 adcs r2, r2
8001baa: 0883 lsrs r3, r0, #2
8001bac: 428b cmp r3, r1
8001bae: d301 bcc.n 8001bb4 <__divsi3+0x190>
8001bb0: 008b lsls r3, r1, #2
8001bb2: 1ac0 subs r0, r0, r3
8001bb4: 4152 adcs r2, r2
8001bb6: d2d9 bcs.n 8001b6c <__divsi3+0x148>
8001bb8: 0843 lsrs r3, r0, #1
8001bba: 428b cmp r3, r1
8001bbc: d301 bcc.n 8001bc2 <__divsi3+0x19e>
8001bbe: 004b lsls r3, r1, #1
8001bc0: 1ac0 subs r0, r0, r3
8001bc2: 4152 adcs r2, r2
8001bc4: 1a41 subs r1, r0, r1
8001bc6: d200 bcs.n 8001bca <__divsi3+0x1a6>
8001bc8: 4601 mov r1, r0
8001bca: 4663 mov r3, ip
8001bcc: 4152 adcs r2, r2
8001bce: 105b asrs r3, r3, #1
8001bd0: 4610 mov r0, r2
8001bd2: d301 bcc.n 8001bd8 <__divsi3+0x1b4>
8001bd4: 4240 negs r0, r0
8001bd6: 2b00 cmp r3, #0
8001bd8: d500 bpl.n 8001bdc <__divsi3+0x1b8>
8001bda: 4249 negs r1, r1
8001bdc: 4770 bx lr
8001bde: 4663 mov r3, ip
8001be0: 105b asrs r3, r3, #1
8001be2: d300 bcc.n 8001be6 <__divsi3+0x1c2>
8001be4: 4240 negs r0, r0
8001be6: b501 push {r0, lr}
8001be8: 2000 movs r0, #0
8001bea: f000 f805 bl 8001bf8 <__aeabi_idiv0>
8001bee: bd02 pop {r1, pc}
08001bf0 <__aeabi_idivmod>:
8001bf0: 2900 cmp r1, #0
8001bf2: d0f8 beq.n 8001be6 <__divsi3+0x1c2>
8001bf4: e716 b.n 8001a24 <__divsi3>
8001bf6: 4770 bx lr
08001bf8 <__aeabi_idiv0>:
8001bf8: 4770 bx lr
8001bfa: 46c0 nop ; (mov r8, r8)
08001bfc <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8001bfc: 480c ldr r0, [pc, #48] ; (8001c30 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8001bfe: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8001c00: 2100 movs r1, #0
b LoopCopyDataInit
8001c02: e003 b.n 8001c0c <LoopCopyDataInit>
08001c04 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8001c04: 4b0b ldr r3, [pc, #44] ; (8001c34 <LoopForever+0x6>)
ldr r3, [r3, r1]
8001c06: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8001c08: 5043 str r3, [r0, r1]
adds r1, r1, #4
8001c0a: 3104 adds r1, #4
08001c0c <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
8001c0c: 480a ldr r0, [pc, #40] ; (8001c38 <LoopForever+0xa>)
ldr r3, =_edata
8001c0e: 4b0b ldr r3, [pc, #44] ; (8001c3c <LoopForever+0xe>)
adds r2, r0, r1
8001c10: 1842 adds r2, r0, r1
cmp r2, r3
8001c12: 429a cmp r2, r3
bcc CopyDataInit
8001c14: d3f6 bcc.n 8001c04 <CopyDataInit>
ldr r2, =_sbss
8001c16: 4a0a ldr r2, [pc, #40] ; (8001c40 <LoopForever+0x12>)
b LoopFillZerobss
8001c18: e002 b.n 8001c20 <LoopFillZerobss>
08001c1a <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
8001c1a: 2300 movs r3, #0
str r3, [r2]
8001c1c: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001c1e: 3204 adds r2, #4
08001c20 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8001c20: 4b08 ldr r3, [pc, #32] ; (8001c44 <LoopForever+0x16>)
cmp r2, r3
8001c22: 429a cmp r2, r3
bcc FillZerobss
8001c24: d3f9 bcc.n 8001c1a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8001c26: f7ff faad bl 8001184 <SystemInit>
/* Call static constructors */
// bl __libc_init_array
/* Call the application's entry point.*/
bl main
8001c2a: f7fe faf6 bl 800021a <main>
08001c2e <LoopForever>:
LoopForever:
b LoopForever
8001c2e: e7fe b.n 8001c2e <LoopForever>
ldr r0, =_estack
8001c30: 20001000 .word 0x20001000
ldr r3, =_sidata
8001c34: 08001c64 .word 0x08001c64
ldr r0, =_sdata
8001c38: 20000000 .word 0x20000000
ldr r3, =_edata
8001c3c: 20000094 .word 0x20000094
ldr r2, =_sbss
8001c40: 20000094 .word 0x20000094
ldr r3, = _ebss
8001c44: 200003b8 .word 0x200003b8
08001c48 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001c48: e7fe b.n 8001c48 <ADC1_IRQHandler>
...
08001c4c <AHBPrescTable>:
...
8001c54: 0201 0403 0706 0908 ........
08001c5c <APBPrescTable>:
8001c5c: 0000 0000 0201 0403 ........
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