289 lines
8.6 KiB
C
289 lines
8.6 KiB
C
/*
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* This file is part of the libusbhost library
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* hosted at http://github.com/libusbhost/libusbhost
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*
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* Copyright (C) 2015 Amir Hammad <amir.hammad@hotmail.com>
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*
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*
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* libusbhost is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "global.h"
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#include "serial.h"
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#include "cobs.h"
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#include <string.h>
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#include <stdarg.h>
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#include <stdlib.h>
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volatile struct dma_tx_buf usart_tx_buf;
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static uint32_t tx_overruns=0, rx_overruns=0;
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static uint32_t rx_framing_errors=0, rx_protocol_errors=0;
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static struct cobs_decode_state cobs_state;
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static volatile uint8_t rx_buf[32];
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static void usart_schedule_dma(void);
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static int usart_putc_nonblocking(uint8_t c);
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void usart_dma_init() {
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usart_tx_buf.xfr_start = -1;
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usart_tx_buf.xfr_end = 0;
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usart_tx_buf.wr_pos = 0;
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usart_tx_buf.wr_idx = 0;
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usart_tx_buf.cur_packet = -1;
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usart_tx_buf.retransmit_rq = 0;
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usart_tx_buf.wraparound = 0;
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for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
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usart_tx_buf.packet_end[i] = -1;
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cobs_decode_incremental_initialize(&cobs_state);
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/* Configure DMA 1 Channel 2 to handle uart transmission */
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DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR);
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DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos)
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| DMA_CCR_DIR
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| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
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| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
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| DMA_CCR_MINC
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| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
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DMA1_Channel3->CMAR = (uint32_t)&(CRC->DR);
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DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos)
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| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
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| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
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| DMA_CCR_PINC
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| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
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/* triggered on transfer completion. We use this to process the ADC data */
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5);
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USART1->CR1 = /* 8-bit -> M1, M0 clear */
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/* OVER8 clear. Use default 16x oversampling */
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/* CMIF clear */
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USART_CR1_MME
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/* WAKE clear */
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/* PCE, PS clear */
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| USART_CR1_RXNEIE /* Enable receive interrupt */
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/* other interrupts clear */
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| USART_CR1_TE
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| USART_CR1_RE;
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/* Set divider for 115.2kBd @48MHz system clock. */
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//USART1->BRR = 417;
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//USART1->BRR = 48; /* 1MBd */
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//USART1->BRR = 96; /* 500kBd */
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USART1->BRR = 192; /* 250kBd */
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//USART1->BRR = 208; /* 230400 */
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USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV;
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USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */
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/* Enable receive interrupt */
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NVIC_EnableIRQ(USART1_IRQn);
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NVIC_SetPriority(USART1_IRQn, 3<<5);
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/* And... go! */
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USART1->CR1 |= USART_CR1_UE;
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}
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void USART1_IRQHandler() {
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uint32_t isr = USART1->ISR;
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if (isr & USART_ISR_ORE) {
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USART1->ICR = USART_ICR_ORECF;
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rx_overruns++;
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return;
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}
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if (isr & USART_ISR_RXNE) {
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uint8_t c = USART1->RDR;
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int rc = cobs_decode_incremental(&cobs_state, (char *)rx_buf, sizeof(rx_buf), c);
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if (rc == 0) /* packet still incomplete */
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return;
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if (rc < 0) {
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rx_framing_errors++;
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return;
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}
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/* A complete frame received */
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if (rc != 2) {
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rx_protocol_errors++;
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return;
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}
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volatile struct ctrl_pkt *pkt = (volatile struct ctrl_pkt *)rx_buf;
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switch (pkt->type) {
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case CTRL_PKT_RESET:
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for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++)
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usart_tx_buf.packet_end[i] = -1;
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break;
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case CTRL_PKT_ACK:
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if (usart_ack_packet(pkt->orig_id))
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rx_protocol_errors++;
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break;
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case CTRL_PKT_RETRANSMIT:
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usart_tx_buf.retransmit_rq = 1;
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if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
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usart_schedule_dma();
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break;
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default:
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rx_protocol_errors++;
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}
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return;
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}
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}
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void usart_schedule_dma() {
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/* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ
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* disables. */
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volatile struct dma_tx_buf *buf = &usart_tx_buf;
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ssize_t next_start, next_idx;
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if (buf->wraparound) {
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buf->wraparound = 0;
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next_idx = buf->cur_packet;
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next_start = 0;
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} else if (buf->retransmit_rq) {
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buf->retransmit_rq = 0;
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next_idx = buf->cur_packet;
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next_start = buf->xfr_start;
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} else {
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next_idx = (buf->cur_packet + 1) % ARRAY_LEN(usart_tx_buf.packet_end);
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next_start = buf->xfr_end;
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}
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ssize_t next_end = buf->packet_end[next_idx];
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/* Nothing to trasnmit */
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if (next_end == -1)
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return;
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ssize_t xfr_len;
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if (next_end > next_start) /* no wraparound */
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xfr_len = next_end - next_start;
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else /* wraparound */
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xfr_len = sizeof(buf->data) - next_start; /* schedule transfer until end of buffer */
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buf->xfr_start = next_start;
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buf->xfr_end = (next_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
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buf->cur_packet = next_idx;
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/* initiate transmission of new buffer */
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DMA1_Channel2->CMAR = (uint32_t)(buf->data + next_start);
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DMA1_Channel2->CNDTR = xfr_len;
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DMA1_Channel2->CCR |= DMA_CCR_EN;
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}
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int usart_ack_packet(uint8_t idx) {
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if (idx > ARRAY_LEN(usart_tx_buf.packet_end))
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return -EINVAL;
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if (idx != usart_tx_buf.cur_packet)
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return -EINVAL;
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usart_tx_buf.packet_end[idx] = -1;
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/* If the DMA stream is idle right now, schedule the next transfer */
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if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
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usart_schedule_dma();
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return 0;
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}
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int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) {
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/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
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NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
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if (buf->wr_pos == buf->xfr_start) {
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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return -EBUSY;
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}
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buf->data[buf->wr_pos] = c;
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buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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return 0;
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}
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int usart_putc(uint8_t c) {
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/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
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while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
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/* idle */
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}
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return 0;
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}
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int usart_putc_nonblocking(uint8_t c) {
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return usart_dma_fifo_push(&usart_tx_buf, c);
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}
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void DMA1_Channel2_3_IRQHandler(void) {
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/* Transfer complete */
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DMA1->IFCR |= DMA_IFCR_CTCIF2;
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DMA1_Channel2->CCR &= ~DMA_CCR_EN;
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if (usart_tx_buf.retransmit_rq || usart_tx_buf.wraparound)
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usart_schedule_dma();
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}
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/* len is the packet length including headers */
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int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) {
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if (usart_tx_buf.packet_end[usart_tx_buf.wr_idx] != -1) {
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/* Find a free slot for this packet */
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tx_overruns++;
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return -EBUSY;
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}
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pkt->pid = usart_tx_buf.wr_idx;
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pkt->_pad = 0;
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/* make the value this wonky-ass CRC implementation produces match zlib etc. */
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CRC->CR = CRC_CR_REV_OUT | (1<<CRC_CR_REV_IN_Pos) | CRC_CR_RESET;
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for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++)
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CRC->DR = ((uint8_t *)pkt)[i];
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pkt->crc32 = ~CRC->DR;
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int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len);
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if (rc)
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return rc;
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usart_tx_buf.packet_end[usart_tx_buf.wr_idx] = usart_tx_buf.wr_pos;
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usart_tx_buf.wr_idx = (usart_tx_buf.wr_idx + 1) % ARRAY_LEN(usart_tx_buf.packet_end);
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if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
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usart_schedule_dma();
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return 0;
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}
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