338 lines
10 KiB
C
338 lines
10 KiB
C
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#include <stdbool.h>
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#include <stdint.h>
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#include <assert.h>
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#include <string.h>
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#include <math.h>
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#include <stm32f407xx.h>
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#include <stm32f4_isr.h>
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#include "sr_global.h"
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#include "adc.h"
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#include "spi_flash.h"
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#include "freq_meas.h"
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#include "dsss_demod.h"
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#include "con_usart.h"
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#include "mspdebug_wrapper.h"
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static struct spi_flash_if spif;
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unsigned int sysclk_speed = 0;
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unsigned int apb1_speed = 0;
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unsigned int apb2_speed = 0;
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unsigned int auxclk_speed = 0;
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unsigned int apb1_timer_speed = 0;
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unsigned int apb2_timer_speed = 0;
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struct leds leds;
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ssize_t jt_spi_flash_read_block(void *usr, int addr, size_t len, uint8_t *out);
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void __libc_init_array(void) { /* we don't need this. */ }
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void __assert_func (unused_a const char *file, unused_a int line, unused_a const char *function, unused_a const char *expr) {
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asm volatile ("bkpt");
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while(1) {}
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}
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static void clock_setup(void)
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{
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/* 8MHz HSE clock as PLL source. */
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#define HSE_SPEED 8000000
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/* Divide by 8 -> 1 MHz */
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#define PLL_M 8
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/* Multiply by 336 -> 336 MHz VCO frequency */
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#define PLL_N 336
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/* Divide by 4 -> 84 MHz (max freq for our chip) */
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#define PLL_P 2
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/* Aux clock for USB OTG, SDIO, RNG: divide VCO frequency (336 MHz) by 7 -> 48 MHz (required by USB OTG) */
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#define PLL_Q 7
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if (((RCC->CFGR & RCC_CFGR_SWS_Msk) >> RCC_CFGR_SW_Pos) != 0)
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asm volatile ("bkpt");
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if (RCC->CR & RCC_CR_HSEON)
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asm volatile ("bkpt");
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RCC->CR |= RCC_CR_HSEON;
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while(!(RCC->CR & RCC_CR_HSERDY))
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;
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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/* set voltage scale to 1 for max frequency
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* (0b0) scale 2 for fCLK <= 144 Mhz
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* (0b1) scale 1 for 144 Mhz < fCLK <= 168 Mhz
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*/
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PWR->CR |= PWR_CR_VOS;
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/* set AHB prescaler to /1 (CFGR:bits 7:4) */
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RCC->CFGR |= (0 << RCC_CFGR_HPRE_Pos);
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/* set ABP1 prescaler to 4 -> 42MHz */
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RCC->CFGR |= (5 << RCC_CFGR_PPRE1_Pos);
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/* set ABP2 prescaler to 2 -> 84MHz */
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RCC->CFGR |= (4 << RCC_CFGR_PPRE2_Pos);
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if (RCC->CR & RCC_CR_PLLON)
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asm volatile ("bkpt");
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/* Configure PLL */
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static_assert(PLL_P % 2 == 0);
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static_assert(PLL_P >= 2 && PLL_P <= 8);
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static_assert(PLL_N >= 50 && PLL_N <= 432);
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static_assert(PLL_M >= 2 && PLL_M <= 63);
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static_assert(PLL_Q >= 2 && PLL_Q <= 15);
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uint32_t old = RCC->PLLCFGR & ~(RCC_PLLCFGR_PLLM_Msk
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| RCC_PLLCFGR_PLLN_Msk
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| RCC_PLLCFGR_PLLP_Msk
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| RCC_PLLCFGR_PLLQ_Msk
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| RCC_PLLCFGR_PLLSRC);
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RCC->PLLCFGR = old | (PLL_M<<RCC_PLLCFGR_PLLM_Pos)
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| (PLL_N << RCC_PLLCFGR_PLLN_Pos)
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| ((PLL_P/2 - 1) << RCC_PLLCFGR_PLLP_Pos)
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| (PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
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| RCC_PLLCFGR_PLLSRC; /* select HSE as PLL source */
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RCC->CR |= RCC_CR_PLLON;
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sysclk_speed = HSE_SPEED / PLL_M * PLL_N / PLL_P;
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auxclk_speed = HSE_SPEED / PLL_M * PLL_N / PLL_Q;
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apb1_speed = sysclk_speed / 4;
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apb1_timer_speed = apb1_speed * 2;
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apb2_speed = sysclk_speed / 2;
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apb2_timer_speed = apb2_speed * 2;
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/* Wait for main PLL */
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while(!(RCC->CR & RCC_CR_PLLRDY))
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;
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/* Configure Flash: enable prefetch, insn cache, data cache; set latency = 5 wait states
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* See reference manual (RM0090), Section 3.5.1, Table 10 (p. 80)
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*/
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | (5<<FLASH_ACR_LATENCY_Pos);
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/* Select PLL as system clock source */
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RCC->CFGR &= ~RCC_CFGR_SW_Msk;
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RCC->CFGR |= 2 << RCC_CFGR_SW_Pos;
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/* Wait for clock to switch over */
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk)>>RCC_CFGR_SWS_Pos != 2)
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;
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}
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static void led_setup(void)
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{
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN;
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/* onboard leds */
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GPIOA->MODER |= (1<<GPIO_MODER_MODER6_Pos) | (1<<GPIO_MODER_MODER7_Pos);
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GPIOB->MODER |= (1<<GPIO_MODER_MODER11_Pos) | (1<<GPIO_MODER_MODER12_Pos) | (1<<GPIO_MODER_MODER13_Pos)| (1<<GPIO_MODER_MODER14_Pos);
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GPIOB->BSRR = 0xf << 11;
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}
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static void spi_flash_if_set_cs(bool val) {
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if (val)
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GPIOB->BSRR = 1<<0;
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else
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GPIOB->BSRR = 1<<16;
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}
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static void spi_flash_setup(void)
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{
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
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GPIOB->MODER &= ~GPIO_MODER_MODER3_Msk & ~GPIO_MODER_MODER4_Msk & ~GPIO_MODER_MODER5_Msk & ~GPIO_MODER_MODER0_Msk;
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GPIOB->MODER |= (2<<GPIO_MODER_MODER3_Pos) /* SCK */
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| (2<<GPIO_MODER_MODER4_Pos) /* MISO */
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| (2<<GPIO_MODER_MODER5_Pos) /* MOSI */
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| (1<<GPIO_MODER_MODER0_Pos); /* CS */
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GPIOB->OSPEEDR &= ~GPIO_OSPEEDR_OSPEED3_Msk & ~GPIO_OSPEEDR_OSPEED4_Msk
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& ~GPIO_OSPEEDR_OSPEED5_Msk & ~GPIO_OSPEEDR_OSPEED0_Msk;
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GPIOB->OSPEEDR |= (2<<GPIO_OSPEEDR_OSPEED3_Pos) /* SCK */
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| (2<<GPIO_OSPEEDR_OSPEED4_Pos) /* MISO */
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| (2<<GPIO_OSPEEDR_OSPEED5_Pos) /* MOSI */
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| (2<<GPIO_OSPEEDR_OSPEED0_Pos); /* CS */
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GPIOB->AFR[0] &= ~GPIO_AFRL_AFSEL3_Msk & ~GPIO_AFRL_AFSEL4_Msk & ~GPIO_AFRL_AFSEL5_Msk;
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GPIOB->AFR[0] |= (5<<GPIO_AFRL_AFSEL3_Pos) | (5<<GPIO_AFRL_AFSEL4_Pos) | (5<<GPIO_AFRL_AFSEL5_Pos);
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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RCC->APB2RSTR |= RCC_APB2RSTR_SPI1RST;
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RCC->APB2RSTR &= ~RCC_APB2RSTR_SPI1RST;
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spif_init(&spif, 256, SPI1, &spi_flash_if_set_cs);
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}
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/* SPI flash test routine to be called from gdb */
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#ifdef SPI_FLASH_TEST
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void spi_flash_test(void) {
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spif_clear_mem(&spif);
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uint32_t buf[1024];
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for (size_t addr=0; addr<0x10000; addr += sizeof(buf)) {
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for (size_t i=0; i<sizeof(buf); i+= sizeof(buf[0]))
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buf[i/sizeof(buf[0])] = addr + i;
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spif_write(&spif, addr, sizeof(buf), (char *)buf);
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}
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for (size_t i=0; i<sizeof(buf)/sizeof(buf[0]); i++)
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buf[i] = 0;
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spif_read(&spif, 0x1030, sizeof(buf), (char *)buf);
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asm volatile ("bkpt");
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}
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#endif
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static struct jtag_img_descriptor {
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size_t devmem_img_start;
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size_t spiflash_img_start;
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size_t img_len;
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} jtag_img = {
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.devmem_img_start = 0x00c000,
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.spiflash_img_start = 0x000000,
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.img_len = 0x060000,
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};
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ssize_t jt_spi_flash_read_block(void *usr, int addr, size_t len, uint8_t *out) {
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struct jtag_img_descriptor *desc = (struct jtag_img_descriptor *)usr;
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return spif_read(&spif, desc->spiflash_img_start + addr, len, (char *)out);
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}
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static unsigned int measurement_errors = 0;
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static struct dsss_demod_state demod_state;
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static uint32_t freq_sample_ts = 0;
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static float debug_last_freq = 0;
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int main(void)
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{
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#if DEBUG
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/* PLL clock on MCO2 (pin C9) */
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
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GPIOC->MODER &= ~GPIO_MODER_MODER9_Msk;
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GPIOC->MODER |= (2<<GPIO_MODER_MODER9_Pos);
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GPIOC->AFR[1] &= ~GPIO_AFRH_AFSEL9_Msk;
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GPIOC->OSPEEDR |= (3<<GPIO_OSPEEDR_OSPEED9_Pos);
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RCC->CFGR |= (6<<RCC_CFGR_MCO2PRE_Pos) | (3<<RCC_CFGR_MCO2_Pos);
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#endif
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if (((SCB->CPACR>>20) & 0xf) != 0xf) {
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asm volatile ("bkpt");
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}
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clock_setup();
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con_usart_init();
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con_printf("\033[0m\033[2J\033[HBooting...\r\n");
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led_setup();
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spi_flash_setup();
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adc_init();
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#if DEBUG
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/* TIM1 CC1 (ADC trigger) on pin A8 */
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GPIOA->MODER &= ~GPIO_MODER_MODER8_Msk;
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GPIOA->MODER |= (2<<GPIO_MODER_MODER8_Pos);
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GPIOA->AFR[1] &= ~GPIO_AFRH_AFSEL8_Msk;
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GPIOA->AFR[1] |= 1<<GPIO_AFRH_AFSEL8_Pos;
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GPIOA->MODER |= (1<<GPIO_MODER_MODER11_Pos) | (1<<GPIO_MODER_MODER12_Pos) | (1<<GPIO_MODER_MODER15_Pos);
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#endif
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dsss_demod_init(&demod_state);
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con_printf("Booted.\r\n");
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int i=0;
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while (23) {
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mspd_jtag_init();
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con_printf("%d flash result: %d\r\n", i,
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mspd_jtag_flash_and_reset(jtag_img.devmem_img_start, jtag_img.img_len, jt_spi_flash_read_block, &jtag_img));
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for (int i=0; i<168*1000*5; i++)
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asm volatile ("nop");
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i++;
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}
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while (23) {
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if (adc_fft_buf_ready_idx != -1) {
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for (int i=0; i<168*1000*2; i++)
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asm volatile ("nop");
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GPIOA->BSRR = 1<<11;
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memcpy(adc_fft_buf[!adc_fft_buf_ready_idx], adc_fft_buf[adc_fft_buf_ready_idx] + FMEAS_FFT_LEN/2, sizeof(adc_fft_buf[0][0]) * FMEAS_FFT_LEN/2);
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GPIOA->BSRR = 1<<11<<16;
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GPIOB->ODR ^= 1<<14;
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bool clip_low=false, clip_high=false;
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const int clip_thresh = 100;
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for (size_t i=FMEAS_FFT_LEN/2; i<FMEAS_FFT_LEN; i++) {
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int val = adc_fft_buf[adc_fft_buf_ready_idx][i];
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if (val < clip_thresh)
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clip_low = true;
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if (val > FMEAS_ADC_MAX-clip_thresh)
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clip_high = true;
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}
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GPIOB->ODR = (GPIOB->ODR & ~(3<<11)) | (!clip_low<<11) | (!clip_high<<12);
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for (int i=0; i<168*1000*2; i++)
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asm volatile ("nop");
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GPIOA->BSRR = 1<<11;
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float out;
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if (adc_buf_measure_freq(adc_fft_buf[adc_fft_buf_ready_idx], &out)) {
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con_printf("%012d: measurement error\r\n", freq_sample_ts);
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measurement_errors++;
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GPIOB->BSRR = 1<<13;
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debug_last_freq = NAN;
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} else {
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debug_last_freq = out;
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con_printf("%012d: %2d.%03d Hz\r\n", freq_sample_ts, (int)out, (int)(out * 1000) % 1000);
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/* frequency ok led */
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if (48 < out && out < 52)
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GPIOB->BSRR = 1<<13<<16;
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else
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GPIOB->BSRR = 1<<13;
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GPIOA->BSRR = 1<<12;
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dsss_demod_step(&demod_state, out, freq_sample_ts);
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GPIOA->BSRR = 1<<12<<16;
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}
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GPIOA->BSRR = 1<<11<<16;
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freq_sample_ts++; /* TODO: also increase in case of freq measurement error? */
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adc_fft_buf_ready_idx = -1;
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}
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}
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return 0;
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}
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void NMI_Handler(void) {
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asm volatile ("bkpt #1");
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}
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void HardFault_Handler(void) {
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asm volatile ("bkpt #2");
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}
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void MemManage_Handler(void) {
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asm volatile ("bkpt #3");
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}
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void BusFault_Handler(void) {
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asm volatile ("bkpt #4");
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}
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void UsageFault_Handler(void) {
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asm volatile ("bkpt #5");
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}
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void SVC_Handler(void) {
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asm volatile ("bkpt #6");
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}
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void DebugMon_Handler(void) {
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asm volatile ("bkpt #7");
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}
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void PendSV_Handler(void) {
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asm volatile ("bkpt #8");
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}
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void SysTick_Handler(void) {
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asm volatile ("bkpt #9");
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}
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