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Fixup clock config

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This commit is contained in:
jaseg 2020-03-14 15:12:07 +01:00
parent 1b7ae0aeef
commit 0e8a0d6f78
3 changed files with 88 additions and 37 deletions
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41
controller/fw/src/adc.c
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@ -1,4 +1,6 @@
#include <string.h>
#include <stm32f407xx.h>
#include <stm32f4_isr.h>
@ -9,7 +11,6 @@ uint16_t adc_fft_buf[2][FMEAS_FFT_LEN];
volatile int adc_fft_buf_ready_idx = -1;
static DMA_TypeDef *const adc_dma = DMA2;
static DMA_Stream_TypeDef *const mem_stream = DMA2_Stream1;
static DMA_Stream_TypeDef *const adc_stream = DMA2_Stream0;
static const int dma_adc_channel = 0;
static const int adc_channel = 10;
@ -37,7 +38,7 @@ void adc_init() {
while (adc_stream->CR & DMA_SxCR_EN)
; /* wait for stream to become available */
adc_stream->NDTR = FMEAS_FFT_LEN/2;
adc_stream->PAR = &(ADC1->DR);
adc_stream->PAR = (uint32_t) &(ADC1->DR);
adc_stream->M0AR = (uint32_t) (adc_fft_buf[0] + FMEAS_FFT_LEN/2);
adc_stream->M1AR = (uint32_t) (adc_fft_buf[1] + FMEAS_FFT_LEN/2);
adc_stream->CR = (dma_adc_channel<<DMA_SxCR_CHSEL_Pos) | DMA_SxCR_DBM | (1<<DMA_SxCR_MSIZE_Pos)
@ -60,35 +61,39 @@ void adc_init() {
TIM1->ARR = 1000-1; /* 1ms period */
TIM1->CCR1 = 500-1;
TIM1->BDTR = TIM_BDTR_MOE;
/* DEBUG */
TIM1->DIER = TIM_DIER_CC1IE;
NVIC_EnableIRQ(TIM1_CC_IRQn);
NVIC_SetPriority(TIM1_CC_IRQn, 130);
/* END DEBUG */
TIM1->CR1 = TIM_CR1_CEN;
TIM1->EGR = TIM_EGR_UG;
}
void TIM1_CC_IRQHandler(void) {
TIM1->SR &= ~TIM_SR_CC1IF;
static int foo=0;
foo++;
if (foo == 500) {
foo = 0;
GPIOA->ODR ^= 1<<6;
}
}
void DMA2_Stream0_IRQHandler(void) {
uint8_t isr = (DMA2->LISR >> DMA_LISR_FEIF0_Pos) & 0x3f;
GPIOA->ODR ^= 1<<7;
if (isr & DMA_LISR_TCIF0) { /* Transfer complete */
/* Check we're done processing the old buffer */
if (adc_fft_buf_ready_idx != -1)
panic();
/* Kickoff memory DMA into new buffer */
if (mem_stream->CR & DMA_SxCR_EN)
panic(); /* We should be long done by now. */
adc_dma->LIFCR = 0x3d<<DMA_LISR_FEIF1_Pos;
mem_stream->NDTR = FMEAS_FFT_LEN/2;
int ct = !!(adc_stream->CR & DMA_SxCR_CT);
/* back half of old buffer (that was just written) */
mem_stream->PAR = (uint32_t)(adc_fft_buf[!ct] + FMEAS_FFT_LEN/2);
/* front half of current buffer (whose back half is being written now) */
mem_stream->M0AR = (uint32_t) (adc_fft_buf[ct] + 0);
mem_stream->CR = (1<<DMA_SxCR_MSIZE_Pos) | (1<<DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | DMA_SxCR_PINC
| (0<<DMA_SxCR_PL_Pos) | (2<<DMA_SxCR_DIR_Pos);
mem_stream->CR |= DMA_SxCR_EN;
/* Kickoff FFT */
int ct = !!(adc_stream->CR & DMA_SxCR_CT);
adc_fft_buf_ready_idx = !ct;
}