5 commits

Author	SHA1	Message	Date
jaseg	0fda5c8614	First mainboard layout draft done ... Still missing: mesh hookup, layer interconnect, optical link	2025-01-17 23:51:07 +01:00
jaseg	695b58ef9f	Layout WIP	2025-01-16 18:42:35 +01:00
jaseg	37674158d4	Finish power section	2025-01-15 22:18:55 +01:00
jaseg	6538b159d1	WIP	2025-01-15 21:40:14 +01:00
jaseg	0a4aed147b	Initial commit	2025-01-13 20:39:54 +01:00