jaseg/002
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Polish routing

Browse source
This commit is contained in:
jaseg 2021-02-23 12:51:56 +01:00
parent 44337556e7
commit fc74106bf7
4 changed files with 56566 additions and 19142 deletions
Download patch file Download diff file Expand all files Collapse all files

75678
control_board/control_board.kicad_pcb
View file

File diff suppressed because it is too large Load diff

8
control_board/control_board.kicad_prl
View file

@ -1,7 +1,7 @@
{
"board": {
"active_layer": 31,
"active_layer_preset": "All Layers",
"active_layer_preset": "",
"auto_track_width": false,
"hidden_nets": [],
"high_contrast_mode": 0,
@ -10,7 +10,7 @@
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 1.0
"zones": 0.6000000238418579
},
"ratsnest_display_mode": 0,
"selection_filter": {
@ -63,8 +63,8 @@
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 1
"visible_layers": "7ffffff_80000001",
"zone_display_mode": 0
},
"meta": {
"filename": "control_board.kicad_prl",

8
control_board/control_board.kicad_pro
View file

@ -45,7 +45,7 @@
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
"min_clearance": 0.15
}
},
"diff_pair_dimensions": [
@ -84,8 +84,8 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "error",
"silk_overlap": "error",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -108,7 +108,7 @@
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.127,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,

14
control_board/control_board.kicad_sch
View file

@ -3378,7 +3378,7 @@
)
(wire (pts (xy 105.41 162.56) (xy 105.41 165.1))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 5f9420a6-63fe-47e2-837b-a0e7ebd8f842)
(uuid 62edd333-3453-42ba-8989-8d2d06a7ba9f)
)
(wire (pts (xy 105.41 170.18) (xy 105.41 173.99))
(stroke (width 0) (type solid) (color 0 0 0 0))
@ -4004,7 +4004,7 @@
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 9ef30361-1fb9-46db-b58f-eeb7288567c0)
)
(wire (pts (xy 267.97 198.12) (xy 285.75 198.12))
(wire (pts (xy 267.97 198.12) (xy 278.13 198.12))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 7aef9b25-8ce8-42db-be8d-39d8017f1b7d)
)
@ -4072,9 +4072,17 @@
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 33b2f656-b4ec-49f8-b474-a36c6c0fa00e)
)
(wire (pts (xy 278.13 198.12) (xy 278.13 198.12))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid bfef2ab6-4230-49d8-97d1-bb0b9e2d087a)
)
(wire (pts (xy 278.13 198.12) (xy 278.13 200.66))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 12d19d26-f96d-4de2-8488-af9a5a2359cd)
(uuid bfef2ab6-4230-49d8-97d1-bb0b9e2d087a)
)
(wire (pts (xy 278.13 198.12) (xy 285.75 198.12))
(stroke (width 0) (type solid) (color 0 0 0 0))
(uuid 7aef9b25-8ce8-42db-be8d-39d8017f1b7d)
)
(wire (pts (xy 278.13 205.74) (xy 278.13 208.28))
(stroke (width 0) (type solid) (color 0 0 0 0))