176 lines
No EOL
7.8 KiB
VHDL
176 lines
No EOL
7.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- File: serialiser_10_to_1.vhd
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--
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-- Engineer: Mike Field <hamster@snap.net.nz>
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--
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-- Module Name: serialiser_10_to_1 - Behavioral
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--
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-- Description: Using the OSERDESE2 as a 10:1 serialiser, using a x1 and x5
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-- clocks (using DDR outputs).
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--
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-- The tricky bit is that reset needs to be asserted, and then CE asserted
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-- after the reset or it will not simulate correctly (outputs show as 'X')
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--
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------------------------------------------------------------------------------------
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-- The MIT License (MIT)
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--
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-- Copyright (c) 2015 Michael Alan Field
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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------------------------------------------------------------------------------------
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----- Want to say thanks? ----------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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-- This design has taken many hours - with the industry metric of 30 lines
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-- per day, it is equivalent to about 6 months of work. I'm more than happy
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-- to share it if you can make use of it. It is released under the MIT license,
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-- so you are not under any onus to say thanks, but....
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--
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-- If you what to say thanks for this design how about trying PayPal?
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-- Educational use - Enough for a beer
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-- Hobbyist use - Enough for a pizza
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-- Research use - Enough to take the family out to dinner
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-- Commercial use - A weeks pay for an engineer (I wish!)
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity serialiser_10_to_1 is
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Port ( clk : in STD_LOGIC;
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clk_x5 : in STD_LOGIC;
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data : in STD_LOGIC_VECTOR (9 downto 0);
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reset : in std_logic;
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serial : out STD_LOGIC);
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end serialiser_10_to_1;
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architecture Behavioral of serialiser_10_to_1 is
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signal shift1 : std_logic := '0';
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signal shift2 : std_logic := '0';
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signal ce_delay : std_logic_vector(7 downto 0) := (others => '0');
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signal reset_delay : std_logic_vector(7 downto 0) := (others => '0');
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begin
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master_serdes : OSERDESE2
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generic map (
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DATA_RATE_OQ => "DDR", -- DDR, SDR
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DATA_RATE_TQ => "DDR", -- DDR, BUF, SDR
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DATA_WIDTH => 10, -- Parallel data width (2-8,10,14)
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INIT_OQ => '1', -- Initial value of OQ output (1'b0,1'b1)
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INIT_TQ => '1', -- Initial value of TQ output (1'b0,1'b1)
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SERDES_MODE => "MASTER", -- MASTER, SLAVE
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SRVAL_OQ => '0', -- OQ output value when SR is used (1'b0,1'b1)
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SRVAL_TQ => '0', -- TQ output value when SR is used (1'b0,1'b1)
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TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
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TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)
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TRISTATE_WIDTH => 1 -- 3-state converter width (1,4)
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)
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port map (
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OFB => open, -- 1-bit output: Feedback path for data
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OQ => serial, -- 1-bit output: Data path output
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-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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SHIFTOUT1 => open,
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SHIFTOUT2 => open,
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TBYTEOUT => open, -- 1-bit output: Byte group tristate
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TFB => open, -- 1-bit output: 3-state control
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TQ => open, -- 1-bit output: 3-state control
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CLK => clk_x5, -- 1-bit input: High speed clock
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CLKDIV => clk, -- 1-bit input: Divided clock
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-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
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D1 => data(0),
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D2 => data(1),
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D3 => data(2),
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D4 => data(3),
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D5 => data(4),
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D6 => data(5),
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D7 => data(6),
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D8 => data(7),
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OCE => '1', --ce_delay(0), -- 1-bit input: Output data clock enable
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RST => reset, -- 1-bit input: Reset
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-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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SHIFTIN1 => SHIFT1,
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SHIFTIN2 => SHIFT2,
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-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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T1 => '0',
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T2 => '0',
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T3 => '0',
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T4 => '0',
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TBYTEIN => '0', -- 1-bit input: Byte group tristate
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TCE => '0' -- 1-bit input: 3-state clock enable
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);
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slave_serdes : OSERDESE2
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generic map (
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DATA_RATE_OQ => "DDR", -- DDR, SDR
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DATA_RATE_TQ => "DDR", -- DDR, BUF, SDR
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DATA_WIDTH => 10, -- Parallel data width (2-8,10,14)
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INIT_OQ => '1', -- Initial value of OQ output (1'b0,1'b1)
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INIT_TQ => '1', -- Initial value of TQ output (1'b0,1'b1)
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SERDES_MODE => "SLAVE", -- MASTER, SLAVE
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SRVAL_OQ => '0', -- OQ output value when SR is used (1'b0,1'b1)
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SRVAL_TQ => '0', -- TQ output value when SR is used (1'b0,1'b1)
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TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
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TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)
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TRISTATE_WIDTH => 1 -- 3-state converter width (1,4)
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)
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port map (
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OFB => open, -- 1-bit output: Feedback path for data
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OQ => open, -- 1-bit output: Data path output
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-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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SHIFTOUT1 => shift1,
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SHIFTOUT2 => shift2,
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TBYTEOUT => open, -- 1-bit output: Byte group tristate
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TFB => open, -- 1-bit output: 3-state control
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TQ => open, -- 1-bit output: 3-state control
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CLK => clk_x5, -- 1-bit input: High speed clock
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CLKDIV => clk, -- 1-bit input: Divided clock
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-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
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D1 => '0',
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D2 => '0',
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D3 => data(8),
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D4 => data(9),
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D5 => '0',
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D6 => '0',
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D7 => '0',
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D8 => '0',
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OCE => '1', --ce_delay(0), -- 1-bit input: Output data clock enable
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RST => reset, -- 1-bit input: Reset
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-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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SHIFTIN1 => '0',
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SHIFTIN2 => '0',
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-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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T1 => '0',
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T2 => '0',
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T3 => '0',
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T4 => '0',
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TBYTEIN => '0', -- 1-bit input: Byte group tristate
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TCE => '0' -- 1-bit input: 3-state clock enable
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);
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delay_ce: process(clk_x5)
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begin
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if rising_edge(clk_x5) then
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ce_delay <= not reset & ce_delay(ce_delay'high downto 1);
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end if;
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end process;
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end Behavioral; |