diff --git a/Artix-7-HDMI-processing.xpr b/Artix-7-HDMI-processing.xpr
index 492b92a..bfea4ef 100644
--- a/Artix-7-HDMI-processing.xpr
+++ b/Artix-7-HDMI-processing.xpr
@@ -42,7 +42,7 @@
-
+
diff --git a/spi_core_tb_behav.wcfg b/spi_core_tb_behav.wcfg
deleted file mode 100644
index 96cc0a0..0000000
--- a/spi_core_tb_behav.wcfg
+++ /dev/null
@@ -1,128 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- clk
- clk
-
-
- rst
- rst
-
-
- ncs
- ncs
-
-
- sck
- sck
- #FFFF00
- true
-
-
- sdi
- sdi
- #FFFF00
- true
-
-
- sdo
- sdo
- #FFFF00
- true
-
-
- cs_rising
- cs_rising
-
-
- cs_falling
- cs_falling
-
-
- data_out[15:0]
- data_out[15:0]
-
-
- data_out_valid
- data_out_valid
-
-
- data_in[15:0]
- data_in[15:0]
-
-
- data_in_valid
- data_in_valid
-
-
- sim_txbuf[15:0]
- sim_txbuf[15:0]
- #FAAFBE
- true
-
-
- last_cs
- last_cs
-
-
- last_sck[1:0]
- last_sck[1:0]
- BINARYRADIX
-
-
- rx_buf[15:0]
- rx_buf[15:0]
-
-
- tx_buf[15:0]
- tx_buf[15:0]
-
-
- tx_buf_next[15:0]
- tx_buf_next[15:0]
-
-
- sck_rising
- sck_rising
-
-
- sck_falling
- sck_falling
-
-
- i[31:0]
- i[31:0]
-
-
- sim_rxdata[1:4][15:0]
- sim_rxdata[1:4][15:0]
-
-
- sim_txdata[1:4][15:0]
- sim_txdata[1:4][15:0]
-
-
- testcase[31:0]
- testcase[31:0]
-
-
diff --git a/spi_regfile_tb_behav.wcfg b/spi_regfile_tb_behav.wcfg
index 4735b15..ac56f08 100644
--- a/spi_regfile_tb_behav.wcfg
+++ b/spi_regfile_tb_behav.wcfg
@@ -11,42 +11,56 @@
-
-
-
+
+
+
-
+
testcase[31:0]
testcase[31:0]
+ #DCDCDC
+ true
clk
clk
+ #DCDCDC
+ true
rst
rst
+ #DCDCDC
+ true
sck
sck
+ #FFFF00
+ true
sdi
sdi
+ #FFFF00
+ true
sdo
sdo
+ #FFFF00
+ true
ncs
ncs
+ #FFFF00
+ true
spi_data_in[15:0]
@@ -64,14 +78,14 @@
spi_cmd_word[15:0]
spi_cmd_word[15:0]
-
- spi_cmd_begin
- spi_cmd_begin
-
spi_cmd_active
spi_cmd_active
+
+ spi_cmd_begin
+ spi_cmd_begin
+
spi_cmd_step
spi_cmd_step
@@ -112,69 +126,39 @@
WORDSIZE[31:0]
WORDSIZE[31:0]
-
- data_out[15:0]
- data_out[15:0]
- #FFFF00
- true
-
-
- data_out_valid
- data_out_valid
- #FFFF00
- true
-
-
- data_in[15:0]
- data_in[15:0]
- #FFFF00
- true
-
-
- data_in_valid
- data_in_valid
- #FFFF00
- true
-
-
- sck_rising
- sck_rising
- #FFFF00
- true
-
-
- sck_falling
- sck_falling
- #FFFF00
- true
-
-
- tx_buf[15:0]
- tx_buf[15:0]
- #FFFF00
- true
-
-
- tx_buf_next[15:0]
- tx_buf_next[15:0]
- #FFFF00
- true
-
-
- is_spi_cmd_word
- is_spi_cmd_word
+
+ txbuf[14:0]
+ txbuf[14:0]
#FAAFBE
true
-
- spi_core_cs_rising
- spi_core_cs_rising
+
+ rxbuf[15:0]
+ rxbuf[15:0]
#FAAFBE
true
-
- spi_core_cs_falling
- spi_core_cs_falling
+
+ is_cmd_word
+ is_cmd_word
+ #FAAFBE
+ true
+
+
+ last_ncs
+ last_ncs
+ #FAAFBE
+ true
+
+
+ last_sck
+ last_sck
+ #FAAFBE
+ true
+
+
+ load_data
+ load_data
#FAAFBE
true
diff --git a/src/spi_core.v b/src/spi_core.v
deleted file mode 100644
index 41b66e0..0000000
--- a/src/spi_core.v
+++ /dev/null
@@ -1,89 +0,0 @@
-`timescale 1ns / 1ps
-
-module spi_core(
- input clk, rst,
-
- input sck, sdi, ncs,
- output reg sdo,
-
- output reg cs_rising,
- output reg cs_falling,
- output reg [WORDSIZE-1:0] data_out,
- output reg data_out_valid,
- input [WORDSIZE-1:0] data_in,
- input data_in_valid
-);
-
-parameter WORDSIZE = 16;
-parameter SPI_CPOL = 0;
-parameter SPI_CPHA = 0;
-
-/* Receiver */
-
-reg last_cs;
-reg [1:0] last_sck;
-reg [WORDSIZE-1:0] rx_buf;
-reg [WORDSIZE-1:0] tx_buf;
-reg [WORDSIZE-1:0] tx_buf_next;
-
-wire sck_rising = !last_sck[1] && last_sck[0];
-wire sck_falling = last_sck[1] && !last_sck[0];
-
-always @(posedge clk) begin
- last_cs <= ncs;
- last_sck = {last_sck[0], sck};
- data_out_valid <= 0;
-
- if (rst) begin
- rx_buf[WORDSIZE-1:1] <= 0;
- rx_buf[0] <= 1;
- tx_buf <= 0;
- tx_buf_next <= 0;
- sdo <= 0;
- data_out <= 0;
- data_out_valid <= 0;
-
- end else begin
- if (last_cs && !ncs) begin /* cs falling, device asserted */
- cs_falling <= 1;
- cs_rising <= 0;
- sdo <= tx_buf_next[WORDSIZE-1];
- tx_buf <= {tx_buf_next[WORDSIZE-2:0], 1'b0};
- tx_buf_next <= 0;
-
- end else if (!last_cs && ncs) begin /* cs rising, device de-asserted */
- cs_falling <= 0;
- cs_rising <= 1;
-
- end else begin /* cs unchanged */
- cs_falling <= 0;
- cs_rising <= 0;
- end
-
- if(!ncs) begin
- if (((SPI_CPOL == SPI_CPHA) && sck_rising) || ((SPI_CPOL != SPI_CPHA) && sck_falling)) begin /* sampling edge */
- if (rx_buf[WORDSIZE-1]) begin
- data_out <= {rx_buf[WORDSIZE-2:0], sdi};
- data_out_valid <= 1;
- rx_buf[WORDSIZE-1:1] <= 0;
- rx_buf[0] <= 1;
- tx_buf <= tx_buf_next;
- tx_buf_next <= 0;
-
- end else begin
- rx_buf <= {rx_buf[WORDSIZE-2:0], sdi};
- end
-
- end else if (((SPI_CPOL == SPI_CPHA) && sck_falling) || ((SPI_CPOL != SPI_CPHA) && sck_rising)) begin /* driving edge */
- sdo <= tx_buf[WORDSIZE-1];
- tx_buf <= {tx_buf[WORDSIZE-2:0], 1'b0};
- end
- end
-
- if (data_in_valid) begin
- tx_buf_next <= data_in;
- end
- end
-end
-
-endmodule
diff --git a/src/spi_regfile.v b/src/spi_regfile.v
index f211dac..7c44a53 100644
--- a/src/spi_regfile.v
+++ b/src/spi_regfile.v
@@ -4,7 +4,7 @@ module spi_regfile(
input clk, rst,
input sck, sdi, ncs,
- output sdo,
+ output reg sdo,
input [15:0] spi_data_in,
output reg [15:0] spi_data_out,
@@ -17,69 +17,71 @@ module spi_regfile(
output reg [19:0] spi_cmd_idx
);
-wire spi_core_cs_rising, spi_core_cs_falling;
-reg [15:0] spi_core_data_in;
-reg spi_core_data_in_valid;
-wire [15:0] spi_core_data_out;
-wire spi_core_data_out_valid;
-reg is_spi_cmd_word;
+reg [14:0] txbuf;
+reg [15:0] rxbuf;
+reg is_cmd_word;
+reg last_ncs;
+reg last_sck;
+reg load_data;
always @(posedge clk) begin
- spi_core_data_in_valid <= 0;
spi_cmd_begin <= 0;
spi_cmd_step <= 0;
- spi_core_data_in <= spi_status_word;
+ load_data <= 0;
+ last_ncs <= ncs;
+ last_sck <= sck;
if (rst) begin
- is_spi_cmd_word <= 1;
+ is_cmd_word <= 1;
spi_cmd_active <= 0;
spi_cmd_idx <= 0;
end else begin
-
- if (spi_core_cs_rising) begin
- is_spi_cmd_word <= 1;
- spi_cmd_active <= 0;
+ if (last_ncs && !ncs) begin
+ txbuf <= spi_status_word[14:0];
+ sdo <= spi_status_word[15];
+ rxbuf <= 15'h0001;
end
- if (ncs) begin
- /* constantly refresh status word */
- spi_core_data_in_valid <= 1;
- end
-
- if (spi_core_data_out_valid) begin
- spi_core_data_in <= spi_data_in;
- spi_core_data_in_valid <= 1;
-
- if (is_spi_cmd_word) begin
- spi_cmd_word <= spi_core_data_out;
- spi_cmd_idx <= 0;
- spi_cmd_active <= 1;
- spi_cmd_begin <= 1;
- is_spi_cmd_word <= 0;
+ if (!ncs) begin
+ if (!last_sck && sck) begin /* sampling edge */
+ if (!rxbuf[15]) begin
+ rxbuf <= {rxbuf[14:0], sdi};
+
+ end else begin
+ rxbuf <= 15'h0001;
+ load_data <= 1;
+
+ if (is_cmd_word) begin
+ spi_cmd_word <= {rxbuf[14:0], sdi};
+ is_cmd_word <= 0;
+ spi_cmd_active <= 1;
+ spi_cmd_begin <= 1;
+ spi_cmd_idx <= 0;
+
+ end else begin
+ spi_data_out <= {rxbuf[14:0], sdi};
+ spi_cmd_idx <= spi_cmd_idx+1;
+ spi_cmd_step <= 1;
+ end
+ end
- end else begin
- spi_cmd_idx <= spi_cmd_idx + 1;
- spi_cmd_step <= 1;
- spi_data_out <= spi_core_data_out;
+ end else if (last_sck && !sck) begin /* driving edge */
+ if (load_data) begin
+ sdo <= spi_data_in[15];
+ txbuf <= spi_data_in[14:0];
+
+ end else begin
+ sdo <= txbuf[14];
+ txbuf <= {txbuf[13:0], 1'b0};
+ end
end
+
+ end else begin
+ spi_cmd_active <= 0;
end
end
end
-spi_core #(.WORDSIZE(16)) spi_core_dut (
- .clk(clk), .rst(rst),
-
- .sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
-
- .cs_rising(spi_core_cs_rising),
- .cs_falling(spi_core_cs_falling),
-
- .data_out(spi_core_data_out),
- .data_out_valid(spi_core_data_out_valid),
- .data_in(spi_core_data_in),
- .data_in_valid(spi_core_data_in_valid)
-);
-
endmodule
diff --git a/test_bench/spi_core_tb.v b/test_bench/spi_core_tb.v
deleted file mode 100644
index 4a2e6a2..0000000
--- a/test_bench/spi_core_tb.v
+++ /dev/null
@@ -1,146 +0,0 @@
-`timescale 1ns / 1ps
-
-module spi_core_tb();
-
-localparam period = 10;
-parameter WORDSIZE = 16;
-reg clk, rst;
-
-reg sck, sdi, ncs;
-wire sdo;
-
-wire cs_rising, cs_falling;
-
-wire [WORDSIZE-1:0] data_out;
-wire data_out_valid;
-
-reg [WORDSIZE-1:0] data_in;
-reg data_in_valid;
-
-initial begin
- clk = 0;
- /* rst set below */
- sck = 0;
- sdi = 0;
- ncs = 1;
- data_in = 0;
- data_in_valid = 0;
- forever #period clk = ~clk;
-end
-
-integer i;
-integer j;
-integer k;
-integer testcase;
-reg [WORDSIZE-1:0] sim_rxdata [1:4];
-reg [WORDSIZE-1:0] sim_txdata [1:4];
-reg [WORDSIZE-1:0] sim_txbuf;
-initial begin
- sim_rxdata[1] = 16'h523a;
- sim_rxdata[2] = 16'hbeef;
- sim_rxdata[3] = 16'h7721;
- sim_rxdata[4] = 16'h0108;
-
- sim_txdata[1] = 16'h1234;
- sim_txdata[2] = 16'h5678;
- sim_txdata[3] = 16'h9abc;
- sim_txdata[4] = 16'hdef9;
-
- for (j=1; j<=4; j=j+1) begin
- $display("TC-SIMPLE-%d: rx/tx %d word", j, j);
- testcase = j;
-
- rst = 1;
- repeat(2) @(posedge clk);
- rst = 0;
- @(posedge clk);
-
- data_in = sim_txdata[1];
- data_in_valid = 1;
- @(posedge clk);
-
- data_in_valid = 0;
- ncs = 0;
- @(posedge clk);
- if (cs_rising || !cs_falling || data_out_valid) $finish;
-
- for (k=0; k 0 && spi_cmd_begin) $finish;
- if (k == 0 && spi_cmd_step) $finish;
- if (k > 0 && !spi_cmd_step) $finish;
+ if (k == 1 && !spi_cmd_begin) $finish;
+ if (k > 1 && spi_cmd_begin) $finish;
+ if (k == 1 && spi_cmd_step) $finish;
+ if (k > 1 && !spi_cmd_step) $finish;
if (spi_cmd_word != sim_rxdata[1]) $finish;
- if (k > 0 && spi_data_out != sim_rxdata[k+1]) $finish;
- if (k == 0 && sim_txbuf != 16'h3141) $finish;
- if (k > 0 && sim_txbuf != sim_txdata[k]) $finish;
+ if (k > 1 && spi_data_out != sim_rxdata[k]) $finish;
+ if (k == 1 && sim_txbuf != 16'h3141) $finish;
+ if (k > 1 && sim_txbuf != sim_txdata[k]) $finish;
+ if (spi_cmd_idx != k-1) $finish;
end
sck = 0;
@(posedge clk);
ncs = 1;
@(posedge clk);
- @(posedge clk);
if (spi_cmd_active) $finish;
if (spi_cmd_step) $finish;