diff --git a/Artix-7-HDMI-processing.xpr b/Artix-7-HDMI-processing.xpr
index 0ed0757..f7156a8 100644
--- a/Artix-7-HDMI-processing.xpr
+++ b/Artix-7-HDMI-processing.xpr
@@ -133,6 +133,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/src/symbol_dump.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/src/pixel_processing.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -151,13 +157,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/src/symbol_dump.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="hdmi_design"/>
diff --git a/src/edge_enhance.vhd b/src/edge_enhance.vhd
index 480e5bc..e74afe7 100644
--- a/src/edge_enhance.vhd
+++ b/src/edge_enhance.vhd
@@ -206,25 +206,24 @@ process(clk)
                 out_hsync <= sobel_3_hsync;
                 out_blank <= sobel_3_blank;
                 out_vsync <= sobel_3_vsync;
-                
-                if sobel_3_red(12 downto 11) = "00" then
-                    out_red   <= std_logic_vector(sobel_3_red(10 downto 3));
+
+                if sobel_3_red(12 downto 12) = "0" then
+                    out_red   <= std_logic_vector(sobel_3_red(11 downto 4));
                 else
                     out_red   <= (others => '1');
                 end if;
 
-                if sobel_3_green(12 downto 11) = "00" then
-                    out_green   <= std_logic_vector(sobel_3_green(10 downto 3));
+                if sobel_3_green(12 downto 12) = "0" then
+                    out_green   <= std_logic_vector(sobel_3_green(11 downto 4));
                 else
                     out_green   <= (others => '1');
                 end if;
 
-                if sobel_3_blue(12 downto 11) = "00" then
-                    out_blue   <= std_logic_vector(sobel_3_blue(10 downto 3));
+                if sobel_3_blue(12 downto 12) = "0" then
+                    out_blue   <= std_logic_vector(sobel_3_blue(11 downto 4));
                 else
                     out_blue   <= (others => '1');
                 end if;
-                
             else
                 out_hsync <= bypass_3_hsync;
                 out_blank <= bypass_3_blank;
diff --git a/src/hdmi_design.vhd b/src/hdmi_design.vhd
index 47cf2e3..118cffa 100644
--- a/src/hdmi_design.vhd
+++ b/src/hdmi_design.vhd
@@ -334,14 +334,14 @@ i_processing: pixel_processing Port map (
 
     -- Swap to this if you want to capture the HDMI symbols
     -- and send them up the RS232 port
-    rs232_tx <= '1';
---i_symbol_dump: symbol_dump port map (
---            clk         => pixel_clk,
---            clk100      => clk100,
---            symbol_sync => symbol_sync,
---            symbol_ch0  => symbol_ch0,
---            symbol_ch1  => symbol_ch1,
---            symbol_ch2  => symbol_ch2, 
---            rs232_tx    => rs232_tx);        
+    --rs232_tx <= '1';
+i_symbol_dump: symbol_dump port map (
+            clk         => pixel_clk,
+            clk100      => clk100,
+            symbol_sync => symbol_sync,
+            symbol_ch0  => symbol_ch0,
+            symbol_ch1  => symbol_ch1,
+            symbol_ch2  => symbol_ch2, 
+            rs232_tx    => rs232_tx);        
     
 end Behavioral;
\ No newline at end of file