From 66d6b029c8f1d359a87961216803ecdba3efc19d Mon Sep 17 00:00:00 2001
From: Mike Field <hamster@snap.net.nz>
Date: Thu, 6 Aug 2015 23:25:22 +1200
Subject: [PATCH] Added on-screen rule of 1/3rds guidelines.

NOTE: Do not yet work correctly for 1080i.
---
 Artix-7-HDMI-processing.xpr |  31 ++++---
 README.txt                  |   6 +-
 constraints/NexysVideo.xdc  |  10 +--
 src/guidelines.vhd          | 162 ++++++++++++++++++++++++++++++++++++
 src/hdmi_design.vhd         |   4 +-
 src/pixel_processing.vhd    |  76 +++++++++++++++--
 6 files changed, 262 insertions(+), 27 deletions(-)
 create mode 100644 src/guidelines.vhd

diff --git a/Artix-7-HDMI-processing.xpr b/Artix-7-HDMI-processing.xpr
index bf15b88..eab609a 100644
--- a/Artix-7-HDMI-processing.xpr
+++ b/Artix-7-HDMI-processing.xpr
@@ -9,6 +9,7 @@
     <Option Name="Id" Val="487e6670b2224898a3f8937139078585"/>
     <Option Name="Part" Val="xc7a200tfbg484-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
     <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
@@ -54,6 +55,18 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/src/audio_to_db.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/src/audio_meters.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/src/detect_interlace.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -96,24 +109,18 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/src/audio_to_db.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/src/audio_meters.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PPRDIR/src/hdmi_input.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/src/guidelines.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/src/pixel_processing.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
diff --git a/README.txt b/README.txt
index f12a2bc..51ec522 100644
--- a/README.txt
+++ b/README.txt
@@ -21,6 +21,10 @@ Colourspaces / formats:
  - YCbCr 444
  - YCbCr 422
 
+New feature 6-AUG-2015!
+-----------------------
+Switch 0 will turn guidelines off and on. Will only show in 1080p 1080i and 720p resolutions.
+
 Supported Boards
 ----------------
  - Digilent Nexys Video 
@@ -50,7 +54,7 @@ Known issues:
 
  - There are timings errors, as generating 148.5MHz HDMI using the Artix-7 chip
    is actualy out of spec. Expect seven failing paths and about 20ns of negative 
-   slack
+   slack.
 
 ------------------------------------------------------------------------------------
 -- The MIT License (MIT)
diff --git a/constraints/NexysVideo.xdc b/constraints/NexysVideo.xdc
index c0c20d6..fcc733e 100644
--- a/constraints/NexysVideo.xdc
+++ b/constraints/NexysVideo.xdc
@@ -52,11 +52,11 @@ set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS33 } [get_ports { debug_
 set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS25 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]
 set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS25 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
 set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS25 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
-#set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS25 } [get_ports { switches[3] }]; #IO_L24N_T3_16 Sch=sw[3]
-#set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS25 } [get_ports { switches[4] }]; #IO_L6P_T0_15 Sch=sw[4]
-#set_property -dict { PACKAGE_PIN J16  } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]
-#set_property -dict { PACKAGE_PIN K13  } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]
-#set_property -dict { PACKAGE_PIN M17  } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]
+set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS25 } [get_ports { sw[3] }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS25 } [get_ports { sw[4] }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS25 } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]
+set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS25 } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS25 } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]
 
 ##LEDs
 set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { led[0] }]; #IO_L15P_T2_DQS_13 Sch=led[0]
diff --git a/src/guidelines.vhd b/src/guidelines.vhd
new file mode 100644
index 0000000..710ad4e
--- /dev/null
+++ b/src/guidelines.vhd
@@ -0,0 +1,162 @@
+----------------------------------------------------------------------------------
+-- Engineer: Mike Field <hamster@snap.net.nz> 
+-- 
+-- Module Name: guidelines - Behavioral
+--
+-- Description: When enabled, put guidelines on the screen  
+-- 
+-- The MIT License (MIT)
+-- 
+-- Copyright (c) 2015 Michael Alan Field
+-- 
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+-- 
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+-- 
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+------------------------------------------------------------------------------------
+----- Want to say thanks? ----------------------------------------------------------
+------------------------------------------------------------------------------------
+--
+-- This design has taken many hours - with the industry metric of 30 lines
+-- per day, it is equivalent to about 6 months of work. I'm more than happy
+-- to share it if you can make use of it. It is released under the MIT license,
+-- so you are not under any onus to say thanks, but....
+-- 
+-- If you what to say thanks for this design how about trying PayPal?
+--  Educational use - Enough for a beer
+--  Hobbyist use    - Enough for a pizza
+--  Research use    - Enough to take the family out to dinner
+--  Commercial use  - A weeks pay for an engineer (I wish!)
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity guidelines is
+    Port ( clk : in STD_LOGIC;
+       enable_feature   : in std_logic;
+       -------------------------------
+       -- VGA data recovered from HDMI
+       -------------------------------
+       in_blank  : in std_logic;
+       in_hsync  : in std_logic;
+       in_vsync  : in std_logic;
+       in_red    : in std_logic_vector(7 downto 0);
+       in_green  : in std_logic_vector(7 downto 0);
+       in_blue   : in std_logic_vector(7 downto 0);
+       is_interlaced   : in std_logic;
+       is_second_field : in std_logic;
+        
+       -----------------------------------
+       -- VGA data to be converted to HDMI
+       -----------------------------------
+       out_blank : out std_logic;
+       out_hsync : out std_logic;
+       out_vsync : out std_logic;
+       out_red   : out std_logic_vector(7 downto 0);
+       out_green : out std_logic_vector(7 downto 0);
+       out_blue  : out std_logic_vector(7 downto 0));
+end guidelines;
+
+architecture Behavioral of guidelines is
+    signal hcount : unsigned(11 downto 0) := (others => '0');
+    signal vcount : unsigned(11 downto 0) := (others => '0');
+    signal h_size : unsigned(11 downto 0) := (others => '0');
+    signal v_size : unsigned(11 downto 0) := (others => '0');
+    signal last_blank : std_logic := '0';
+    signal last_vsync : std_logic := '0';
+begin
+
+process(clk)
+    begin
+        if rising_edge(clk) then
+            out_blank  <= in_blank;
+            out_hsync  <= in_hsync;
+            out_vsync  <= in_vsync;
+            out_red    <= in_red;
+            out_green  <= in_green;
+            out_blue   <= in_blue;
+            
+            if enable_feature = '1' then
+                if h_size = 1280 then
+                    if hcount = 426 or hcount = 854 then
+                        out_red   <= (others => '1');
+                        out_green <= (others => '1');
+                        out_blue  <= (others => '1');
+                    end if; 
+                end if; 
+
+                if h_size = 1920 then
+                    if hcount = 640 or hcount = 1280 then
+                        out_red   <= (others => '1');
+                        out_green <= (others => '1');
+                        out_blue  <= (others => '1');
+                    end if; 
+                end if;
+
+                if v_size = 720 then
+                    if vcount = 240 or vcount = 480 then
+                        out_red   <= (others => '1');
+                        out_green <= (others => '1');
+                        out_blue  <= (others => '1');
+                    end if;
+                end if;
+
+                if v_size = 1080 then
+                    if is_interlaced = '0' and (vcount = 360 or vcount = 720) then
+                        out_red   <= (others => '1');
+                        out_green <= (others => '1');
+                        out_blue  <= (others => '1');
+                    end if;
+                    
+                    if is_interlaced = '1' and (vcount = 180 or vcount = 360) then
+                        out_red   <= (others => '1');
+                        out_green <= (others => '1');
+                        out_blue  <= (others => '1');
+                    end if;
+                end if;
+            end if;
+                            
+            -- Count the number of lines in a frame (not field!!!)
+            if last_blank = '0' and in_blank = '1' then
+                vcount <= vcount + 1;
+            end if;
+            -- Use the falling edge of VSYNC to to capture the number of 
+            -- lines on the screen, as the rising edge is where the 
+            -- interaced field is detected and can be a bit unstable.
+            if in_vsync = '0' and last_vsync = '1' and is_second_field = '0'then
+                vcount <= (others => '0');
+                v_size <= vcount;
+            end if;
+
+            -- Count the width of the frame
+            if in_blank = '1' then
+                if hcount /= 0 then
+                    h_size <= hcount;
+                end if;
+                hcount <= (others => '0');
+            else
+                hcount <= hcount + 1;
+            end if;
+            last_blank <= in_blank;
+            last_vsync <= in_vsync;
+            if enable_feature = '1' and in_blank = '0' then
+            end if; 
+        end if;
+    end process;
+end Behavioral;
diff --git a/src/hdmi_design.vhd b/src/hdmi_design.vhd
index 4f9296d..ccfc267 100644
--- a/src/hdmi_design.vhd
+++ b/src/hdmi_design.vhd
@@ -57,7 +57,7 @@ entity hdmi_design is
         clk100    : in STD_LOGIC;
         -- Control signals
         led           : out   std_logic_vector(7 downto 0) :=(others => '0');
-        sw            : in    std_logic_vector(2 downto 0) :=(others => '0');
+        sw            : in    std_logic_vector(7 downto 0) :=(others => '0');
         debug_pmod    : out   std_logic_vector(7 downto 0) :=(others => '0');
 
         --HDMI input signals
@@ -153,6 +153,7 @@ architecture Behavioral of hdmi_design is
     
     component pixel_processing is
         Port ( clk : in STD_LOGIC;
+            switches  : in std_logic_vector(7 downto 0);
             ------------------
             -- Incoming pixels
             ------------------
@@ -271,6 +272,7 @@ i_hdmi_io: hdmi_io port map (
     
 i_processing: pixel_processing Port map ( 
         clk => pixel_clk,
+        switches => sw,
         ------------------
         -- Incoming pixels
         ------------------
diff --git a/src/pixel_processing.vhd b/src/pixel_processing.vhd
index 66895f8..ce46a46 100644
--- a/src/pixel_processing.vhd
+++ b/src/pixel_processing.vhd
@@ -75,8 +75,12 @@ entity pixel_processing is
             ------------------------------------
             audio_channel : in std_logic_vector(2 downto 0);
             audio_de      : in std_logic;
-            audio_sample  : in std_logic_vector(23 downto 0)
-        
+            audio_sample  : in std_logic_vector(23 downto 0);
+      
+            ----------------------------------
+            -- Controls
+            ----------------------------------   
+            switches : in std_logic_vector(7 downto 0)
     );
 end pixel_processing;
 
@@ -128,6 +132,40 @@ architecture Behavioral of pixel_processing is
     );
     end component;
 
+    component guidelines is
+    Port ( clk : in STD_LOGIC;
+           enable_feature   : in std_logic;
+           -------------------------------
+           -- VGA data recovered from HDMI
+           -------------------------------
+           in_blank  : in std_logic;
+           in_hsync  : in std_logic;
+           in_vsync  : in std_logic;
+           in_red    : in std_logic_vector(7 downto 0);
+           in_green  : in std_logic_vector(7 downto 0);
+           in_blue   : in std_logic_vector(7 downto 0);
+           is_interlaced   : in std_logic;
+           is_second_field : in std_logic;
+            
+           -----------------------------------
+           -- VGA data to be converted to HDMI
+           -----------------------------------
+           out_blank : out std_logic;
+           out_hsync : out std_logic;
+           out_vsync : out std_logic;
+           out_red   : out std_logic_vector(7 downto 0);
+           out_green : out std_logic_vector(7 downto 0);
+           out_blue  : out std_logic_vector(7 downto 0)
+    );
+    end component;
+    
+    signal mid_blank : std_logic;
+    signal mid_hsync : std_logic;
+    signal mid_vsync : std_logic;
+    signal mid_red   : std_logic_vector(7 downto 0);
+    signal mid_green : std_logic_vector(7 downto 0);
+    signal mid_blue  : std_logic_vector(7 downto 0);
+
 begin
 
 i_audio_to_db: audio_to_db port map (
@@ -153,16 +191,38 @@ i_audio_meters: audio_meters Port map (
         is_interlaced => is_interlaced,
         is_second_field => is_second_field,
        
-        out_blank => out_blank,
-        out_hsync => out_hsync,
-        out_vsync => out_vsync,
-        out_red   => out_red,
-        out_green => out_green,
-        out_blue  => out_blue,
+        out_blank => mid_blank,
+        out_hsync => mid_hsync,
+        out_vsync => mid_vsync,
+        out_red   => mid_red,
+        out_green => mid_green,
+        out_blue  => mid_blue,
         
         audio_channel => level_channel,
         audio_de      => level_de,
         audio_level   => level
     );
 
+i_guidelines: guidelines Port map ( 
+        clk       => clk,
+        
+        enable_feature => switches(0),
+
+        in_blank  => mid_blank,
+        in_hsync  => mid_hsync,
+        in_vsync  => mid_vsync,
+        in_red    => mid_red,
+        in_green  => mid_green,
+        in_blue   => mid_blue,
+        is_interlaced => is_interlaced,
+        is_second_field => is_second_field,
+       
+        out_blank => out_blank,
+        out_hsync => out_hsync,
+        out_vsync => out_vsync,
+        out_red   => out_red,
+        out_green => out_green,
+        out_blue  => out_blue
+    );
+
  end Behavioral;
\ No newline at end of file