#ifndef __ADC_INTERFACE_H__
#define __ADC_INTERFACE_H__

enum adc_reg_addr {
    ADC_REG_ID = 0x00,
    ADC_REG_STATUS = 0x01,
    ADC_REG_MODE = 0x02,
    ADC_REG_CLOCK = 0x03,
    ADC_REG_GAIN = 0x04,
    ADC_REG_CFG = 0x06,
    ADC_REG_THRSHLD_MSB = 0x07,
    ADC_REG_THRSHLD_LSB = 0x08,
    ADC_REG_CH0_CFG = 0x09,
    ADC_REG_CH0_OCAL_MSB = 0x0a,
    ADC_REG_CH0_OCAL_LSB = 0x0b,
    ADC_REG_CH0_GCAL_MSB = 0x0c,
    ADC_REG_CH0_GCAL_LSB = 0x0d,
    ADC_REG_CH1_CFG = 0x0e,
    ADC_REG_CH1_OCAL_MSB = 0x0f,
    ADC_REG_CH1_OCAL_LSB = 0x10,
    ADC_REG_CH1_GCAL_MSB = 0x11,
    ADC_REG_CH1_GCAL_LSB = 0x12,
    ADC_REG_REGMAP_CRC = 0x3e,
};

#define ADC_STATUS_LOCK         (1<<15)
#define ADC_STATUS_F_RESYNC     (1<<14)
#define ADC_STATUS_REG_MAP      (1<<13)
#define ADC_STATUS_CRC_ERR      (1<<12)
#define ADC_STATUS_CRC_TYPE     (1<<11)
#define ADC_STATUS_RESET        (1<<10)
#define ADC_STATUS_WLENGTH_Pos  8
#define ADC_STATUS_DRDY1        (1<<1)
#define ADC_STATUS_DRDY0        (1<<0)

#define ADC_MODE_REG_CRC_EN     (1<<13)
#define ADC_MODE_RX_CRC_EN      (1<<12)
#define ADC_MODE_CRC_TYPE       (1<<11)
#define ADC_MODE_RESET          (1<<10)
#define ADC_MODE_WLENGTH_Pos    8
#define ADC_MODE_TIMEOUT        (1<<4)
#define ADC_MODE_DRDY_SEL_Pos   2
#define ADC_MODE_DRDY_HiZ       (1<<1)
#define ADC_MODE_DRDY_FMT       (1<<0)

#define ADC_CLOCK_CH1_EN        (1<<9)
#define ADC_CLOCK_CH2_EN        (1<<8)
#define ADC_CLOCK_TBM           (1<<5)
#define ADC_CLOCK_OSR_Pos       2
#define ADC_CLOCK_PWR_Pos       0
#define ADC_CLOCK_OSR_64        ADC_CLOCK_TBM
#define ADC_CLOCK_OSR_128       (0<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_256       (1<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_512       (2<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_1024      (3<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_2048      (4<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_4096      (5<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_8192      (6<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_OSR_16384     (7<<ADC_CLOCK_OSR_Pos)
#define ADC_CLOCK_PWR_VERY_LOW  (0<<ADC_CLOCK_PWR_Pos)
#define ADC_CLOCK_PWR_LOW       (1<<ADC_CLOCK_PWR_Pos)
#define ADC_CLOCK_PWR_HIRES     (2<<ADC_CLOCK_PWR_Pos)

#define ADC_GAIN1_PGAGAIN1_1    (0<<4)
#define ADC_GAIN1_PGAGAIN1_2    (1<<4)
#define ADC_GAIN1_PGAGAIN1_4    (2<<4)
#define ADC_GAIN1_PGAGAIN1_8    (3<<4)
#define ADC_GAIN1_PGAGAIN1_16   (4<<4)
#define ADC_GAIN1_PGAGAIN1_32   (5<<4)
#define ADC_GAIN1_PGAGAIN1_64   (5<<4)
#define ADC_GAIN1_PGAGAIN1_128  (7<<4)
#define ADC_GAIN1_PGAGAIN0_1    (0<<0)
#define ADC_GAIN1_PGAGAIN0_2    (1<<0)
#define ADC_GAIN1_PGAGAIN0_4    (2<<0)
#define ADC_GAIN1_PGAGAIN0_8    (3<<0)
#define ADC_GAIN1_PGAGAIN0_16   (4<<0)
#define ADC_GAIN1_PGAGAIN0_32   (5<<0)
#define ADC_GAIN1_PGAGAIN0_64   (5<<0)
#define ADC_GAIN1_PGAGAIN0_128  (7<<0)

#define ADC_CFG_GC_DLY_Pos      9
#define ADC_CFG_GC_EN           (1<<8)
#define ADC_CFG_CD_ALLCH        (1<<7)
#define ADC_CFG_CD_NUM_Pos      4
#define ADC_CFG_CD_LEN_Pos      1
#define ADC_CFG_CD_EN           (1<<0)

#define ADC_CHn_CFG_PHASE_Pos   6
#define ADC_CHn_CFG_DCBLK_DIS       (1<<2)
#define ADC_CHn_CFG_MUX_Pos         0

#define ADC_FSR_POS 0x7fffff
#define ADC_FSR_NEG -0x800000

#endif /* __ADC_INTERFACE_H__ */