From aee50aaa411424e7a25ca18ebb3d2916786e162f Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.de>
Date: Mon, 24 Apr 2023 20:11:51 +0200
Subject: [PATCH] Fix build, clock init, timer config

---
 Makefile   |  2 +-
 src/main.c | 26 ++++++++++++++------------
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/Makefile b/Makefile
index 2529311..c34fffe 100644
--- a/Makefile
+++ b/Makefile
@@ -76,7 +76,7 @@ CMSIS_DEVICE_DIR_ABS	:= $(abspath $(CMSIS_DEVICE_DIR))
 DEVICE_FAMILY	:= $(shell echo $(DEVICE) | grep -Eio 'STM32[a-z]{1,2}[0-9]'|cut -c 6-)
 DEVICE_DEFINES 	:= -DSTM32$(DEVICE_FAMILY) $(addprefix -D,$(shell cat stm32_buildinfo.defines))
 
-ARCH_FLAGS		?= -mthumb -mcpu=cortex-m4 -mfloat-abi=soft
+ARCH_FLAGS		?= -mthumb -mcpu=cortex-m0 -mfloat-abi=soft
 SYSTEM_FLAGS	?= -nostdlib -ffreestanding -nostartfiles
 
 COMMON_CFLAGS	+= -I$(abspath include)
diff --git a/src/main.c b/src/main.c
index 97a667c..0001530 100644
--- a/src/main.c
+++ b/src/main.c
@@ -169,6 +169,7 @@ void adc_sm(bool reset) {
             break;
 
         case ADC_RUNNING:
+            adc_prepare_read_samples();
             break;
     }
 }
@@ -184,11 +185,11 @@ void adc_init() {
     DMA1_Channel1->CPAR = (uint32_t)&(DMA1_Channel3->CCR);
     DMA1_Channel1->CNDTR = 1;
     /* CH2 -> RX DMA: 8 bit peripheral -> 8 bit memory */
-    DMA1_Channel2->CCR = (0<<DMA_CCR_MSIZE_Pos) | (0<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_TEIE | DMA_CCR_TCIE | DMA_CCR_CIRC;
+    DMA1_Channel2->CCR = (0<<DMA_CCR_MSIZE_Pos) | (0<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_TEIE | DMA_CCR_CIRC;
     DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR);
     DMA1_Channel2->CMAR = (uint32_t)&st_adc.rxbuf;
     /* CH3 -> TX DMA: 8 bit memory -> 8 bit peripheral */
-    DMA1_Channel3->CCR = (0<<DMA_CCR_MSIZE_Pos) | (0<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TEIE | DMA_CCR_TCIE;
+    DMA1_Channel3->CCR = (0<<DMA_CCR_MSIZE_Pos) | (0<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TEIE;
     DMA1_Channel3->CPAR = (uint32_t)&(SPI1->DR);
     DMA1_Channel3->CMAR = (uint32_t)&st_adc.txbuf;
 
@@ -196,9 +197,9 @@ void adc_init() {
     TIM2->CR2 = TIM_CR2_CCDS | (5<<TIM_CR2_MMS_Pos); /* set trigger output to OC2REF */
     TIM2->SMCR = TIM_SMCR_ETP | (7<<TIM_SMCR_TS_Pos) | (6<<TIM_SMCR_SMS_Pos);
     TIM2->DIER = TIM_DIER_CC3DE;
-    TIM2->CCMR1 = (6<<TIM_CCMR1_OC2M_Pos);
+    TIM2->CCMR1 = (0<<TIM_CCMR1_CC1S_Pos) | (7<<TIM_CCMR1_OC2M_Pos);
     TIM2->CCER = TIM_CCER_CC1E;
-    TIM2->CCR2 = 4; /* ~CS pulse */
+    TIM2->CCR2 = 1; /* ~CS pulse */
     TIM2->ARR = 32; /* Time to TX DMA request */
 
     st_adc.dma_ccr3 = DMA1_Channel3->CCR | DMA_CCR_EN;
@@ -208,9 +209,10 @@ void adc_init() {
 
 void DMA1_Channel1_IRQHandler() {
     int flags = DMA1->ISR;
-    if (flags & DMA_ISR_TEIF1) {
+    if (flags & (DMA_ISR_TEIF1)) {
         DMA1->IFCR = DMA_IFCR_CTEIF1;
         asm volatile ("bkpt");
+
     }
 }
 
@@ -219,11 +221,13 @@ void DMA1_Channel2_3_IRQHandler() {
     if (flags & (DMA_ISR_TEIF2 | DMA_ISR_TEIF3)) {
         DMA1->IFCR = DMA_IFCR_CTEIF2 | DMA_IFCR_CTEIF3;
         asm volatile ("bkpt");
+
     } else if (flags & DMA_ISR_TCIF2) {
         DMA1->IFCR = DMA_IFCR_CTCIF2;
         /* measurements ready */
         st_adc.data[0] = (st_adc.rxbuf[4] << 16) | (st_adc.rxbuf[5] << 8) | st_adc.rxbuf[6];
         st_adc.data[1] = (st_adc.rxbuf[7] << 16) | (st_adc.rxbuf[8] << 8) | st_adc.rxbuf[9];
+        adc_sm(false);
     }
 }
 
@@ -292,11 +296,11 @@ void adc_setup_dma(size_t tx_bytes, size_t response_bytes) {
 }
 
 int main(void) {
-
     /* Enable HSE w/ 8 MHz crystal */
     RCC->CR |= RCC_CR_HSEON;
     while (!(RCC->CR & RCC_CR_HSERDY))
         ;
+    asm volatile ("bkpt");
 
     /* Configure PLL multiplier, clock dividers and MCO */
     /* The ADS131M02 datasheet recommends an 8.192 MHz input clock for high-resolution mode. */
@@ -310,11 +314,13 @@ int main(void) {
     RCC->CR |= RCC_CR_PLLON;
     while (!(RCC->CR & RCC_CR_PLLRDY))
         ;
+    asm volatile ("bkpt");
 
     /* Switch system clock to PLL */
     RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
     while (((RCC->CFGR & RCC_CFGR_SWS_Msk) >> RCC_CFGR_SWS_Pos) != 2)
         ;
+    asm volatile ("bkpt");
 
     /* Enable peripheral clocks */
     RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_DMAEN;
@@ -322,6 +328,7 @@ int main(void) {
     RCC->APB1ENR |= RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN | RCC_APB1ENR_SPI2EN | RCC_APB1ENR_USART3EN |
         RCC_APB1ENR_I2C1EN | RCC_APB1ENR_USBEN;
 
+    asm volatile ("bkpt");
     adc_init();
 
 #define AFRL(pin, val) ((val) << ((pin)*4))
@@ -332,12 +339,6 @@ int main(void) {
 #define ANALOG(pin) (3<<(2*(pin)))
 #define CLEAR(pin) (3<<(2*(pin)))
 
-    /* GPIO pin config:
-     * A9: USART 1 TX -> LED
-     * A10: USART 1 RX -> debug
-     * A15: Accelerometer CS
-     * A5/6/7: SPI SCK/MISO/MOSI for Accelerometer
-     */
     /* GPIOA:
      *  0 - !ADC_DRDY
      *  1 -  ADC_SYNC
@@ -405,6 +406,7 @@ int main(void) {
      */
 
     SystemCoreClockUpdate();
+    adc_init();
 //    int apb2_clock = SystemCoreClock / APB2_PRESC;
 //    
 //    TIM15->PSC = apb2_clock / 1000000 * 100 - 1; /* 100us ticks */